公开(公告)号：US20210072586A1

公开(公告)日：2021-03-11

申请号：US16094453

申请日：2018-01-04

Applicant: BOE Technology Group Co., Ltd.

Inventor： Zheng LIU

IPC: G02F1/1333

Abstract: A manufacturing method of a flexible display, a flexible display, and a display device are provided. The method comprises: forming a metal lead on a flexible substrate; bending the flexible substrate and the metal lead; and forming a conductive film layer on the metal lead, which covers at least a bent part of the metal lead.

公开(公告)号：US20190333980A1

公开(公告)日：2019-10-31

申请号：US16468341

申请日：2017-11-06

Applicant: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD. ,  BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Benlian WANG ,  Li WANG ,  Yipeng CHEN ,  Yueping ZUO ,  Zheng LIU

IPC: H01L27/32 ,  H01L51/00 ,  G02F1/1333 ,  G02F1/1362 ,  G02F1/1345

Abstract: A wiring structure, a display substrate and a display device. The wiring structure comprises a plurality of hollow patterns, and edges of the wiring structure along a length direction of the wiring structure extend in a straight line. The wiring structure can release stress through the hollow patterns so as to avoid breakage of the wiring structure, the display substrate, and the display device.

公开(公告)号：US20190097058A1

公开(公告)日：2019-03-28

申请号：US15995706

申请日：2018-06-01

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  FUZHOU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Xiaowei LIU ,  Bo LIU ,  Yang WANG ,  Liangliang LI ,  Zheng LIU ,  Hongjiang WU ,  Jianfeng YUAN

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: Embodiments of the present application provide an Oxide TFT, a manufacturing method thereof, an array substrate and a display device. The Oxide TFT includes a base substrate; a gate electrode, a gate insulating layer and an active layer which are located on the base substrate; a source electrode and a drain electrode, the active layer is at least partly covered with the source electrode and the drain electrode; and a channel protection layer located between the source electrode and the drain electrode, each of the source electrode and the drain electrode includes at least part of a first metallic layer and at least part of a second metallic layer, the first metallic and the second metallic layer are stacked one on another, the channel protection layer is of a metal oxide.

公开(公告)号：US20180211606A1

公开(公告)日：2018-07-26

申请号：US15742723

申请日：2017-05-26

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.

Inventor： Xiaoxiang ZHANG ,  Zheng LIU ,  Huibin GUO ,  Mingxuan LIU

IPC: G09G3/34

CPC classification number: G09G3/34 ,  G09G3/36 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0286

Abstract: A shift register circuit and a driving method therefor, a gate line driving circuit and an array substrate, the shift register circuit includes: a charging sub-circuit for charging a pull-up node under the control of a signal input by an input signal terminal; an output sub-circuit for outputting, through an output terminal, a clock signal provided by a first clock signal terminal to serve as a drive signal, under control of an electric level of the pull-up node; a first pull-down sub-circuit for pulling down the pull-up node and the output terminal under the control of an electric level of a first pull-down node; and a reset sub-circuit for resetting the pull-up node and the output terminal under the control of a reset signal input by a reset signal terminal.

公开(公告)号：US20180203313A1

公开(公告)日：2018-07-19

申请号：US15564661

申请日：2017-05-19

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.

Inventor： Shoukun WANG ,  Huibin GUO ,  Yuchun FENG ,  Liangliang LI ,  Zheng LIU

IPC: G02F1/1362 ,  G02F1/1368 ,  H01L27/12 ,  H01L29/786

CPC classification number: G02F1/136209 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/134372 ,  G02F2001/136222 ,  G02F2201/121 ,  G02F2201/40 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1259 ,  H01L27/1262 ,  H01L29/78633

Abstract: An array substrate, a display device, and a method for manufacturing the array substrate are disclosed. The array substrate includes a base substrate and a pixel array structure disposed on the base substrate, the pixel array structure includes at least one light shielding layer made of a light shielding material, and the light shielding material can prevent light leakage or light reflection, thereby increasing an opening ratio of the display device.

公开(公告)号：US20180122914A1

公开(公告)日：2018-05-03

申请号：US15547643

申请日：2017-01-19

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.

Inventor： Liangliang LI ,  Huibin GUO ,  Zheng LIU ,  Shoukun WANG ,  Yuchun FENG

IPC: H01L29/45 ,  H01L27/12 ,  H01L29/24 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L29/45 ,  G02F1/1368 ,  G02F2001/134318 ,  G02F2001/13685 ,  G02F2201/121 ,  G02F2201/123 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/7869

Abstract: A method of manufacturing a thin-film transistor (TFT) array substrate, including: forming a gate layer, a gate insulating layer, an oxide semiconductor layer, a source/drain electrode layer and a pixel electrode layer on a base substrate. The step of forming the source/drain electrode layer and the pixel electrode layer includes: forming a transparent conductive film and a first metallic film on the oxide semiconductor layer in sequence, to form a stack layer of the transparent conductive film and the first metallic film, in which the transparent conductive film contacts the oxide semiconductor layer; and forming source electrodes, drain electrodes and pixel electrodes by a single patterning process on the stack layer of the transparent conductive film and the first metallic film. One patterning process is saved, the production time is shortened, and the production cost is reduced.

公开(公告)号：US20180108757A1

公开(公告)日：2018-04-19

申请号：US15116980

申请日：2015-10-16

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiaolong LI ,  Zheng LIU ,  Xiaoyong LU ,  Dong LI ,  Chunping LONG

IPC: H01L29/66 ,  H01L21/20 ,  H01L27/12 ,  H01L21/265 ,  H01L29/06 ,  H01L21/28

Abstract: A manufacturing method for a polysilicon thin film is provided. The manufacturing method for a polysilicon thin film includes forming a polysilicon layer, treating a surface of the polysilicon layer so that the surface of the polysilicon layer is electronegative, and supplying polar gas into a process chamber so that polar molecules of the polar gas are adsorbed on the surface of the polysilicon layer which is electronegative so as to form the polysilicon thin film, a surface of which has a hole density higher than an electron density.

公开(公告)号：US20170184892A1

公开(公告)日：2017-06-29

申请号：US15309499

申请日：2016-03-07

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zheng LIU

IPC: G02F1/1368 ,  H01L27/12 ,  H01L21/265 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L29/167 ,  G02F1/1343 ,  H01L29/786

CPC classification number: G02F1/1368 ,  G02F1/134309 ,  G02F1/13439 ,  G02F2001/13685 ,  H01L21/26513 ,  H01L27/1255 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/167 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78675 ,  H01L2029/7863

Abstract: A method for manufacturing an array substrate, including steps of forming a semiconductor pattern, a gate electrode and a first insulation pattern sequentially on a base substrate at different layers, an orthogonal projection of the semiconductor pattern onto the base substrate covering an orthogonal projection of the first insulation pattern onto the base substrate, and the orthogonal projection of the first insulation pattern onto the base substrate covering an orthogonal projection of the gate electrode onto the base substrate, and subjecting the semiconductor pattern to ion implantation through a single ion implantation process using the first insulation pattern and the gate electrode as a mask plate, so as to form an active layer, a heavily-doped source electrode region, a lightly-doped source electrode region, a heavily-doped drain electrode region, and a lightly-doped drain electrode region.

公开(公告)号：US20170162703A1

公开(公告)日：2017-06-08

申请号：US15322490

申请日：2016-03-01

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiaolong LI ,  Zheng LIU ,  Xiaoyong LU ,  Chunping LONG ,  Huijuan ZHANG

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/66 ,  H01L21/04 ,  H01L29/04 ,  H01L29/16

CPC classification number: H01L29/78609 ,  H01L21/02527 ,  H01L21/02598 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/043 ,  H01L29/045 ,  H01L29/1602 ,  H01L29/66045 ,  H01L29/66742 ,  H01L29/78621 ,  H01L29/78684 ,  H01L29/78696

Abstract: The embodiments of present disclosure provide a thin film transistor, a method for manufacturing the same, and an array substrate. The thin film transistor comprises an active layer provided on a substrate, the active layer including a middle channel region, a first high resistance region and a second high resistance region provided respectively on external sides of the middle channel region, a source region provided on an external side of the first high resistance region and a drain region provided on an external side of the second high resistance region, wherein a base material of the active layer is diamond single crystal. According to the thin film transistor, the method for manufacturing the same, and the array substrate provided in the embodiments of present disclosure, by providing high resistance regions on external sides of the middle channel region of the active layer, the carrier mobility is reduced and the leakage current of the thin film transistor made of single crystalline diamond is effectively suppressed.

公开(公告)号：US20170018652A1

公开(公告)日：2017-01-19

申请号：US15122066

申请日：2016-02-22

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zheng LIU ,  Xiaoyong LU ,  Xiaolong LI ,  Yu-Cheng CHAN

IPC: H01L29/786 ,  H01L27/12

CPC classification number: H01L29/78621 ,  H01L27/02 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/66757 ,  H01L29/786 ,  H01L29/78645 ,  H01L29/78675 ,  H01L29/78696

Abstract: A method for fabricating a Polysilicon Thin-Film Transistor is provided. The method includes forming a polysilicon active layer, forming a first gate insulation layer and a first gate electrode sequentially on the active layer, conducting a first ion implantation process on the active layer by using the first gate electrode as a mask to form two doped regions at ends of the active layer, forming a second gate insulation layer and a second gate electrode sequentially on the first gate insulation layer and the first gate electrode, and conducting a second ion implantation process on the active layer by using the second gate electrode as another mask to form two source/drain implantation regions at two outer sides of the doped regions of the active layer. Accordingly, impurity concentration of the two doped regions is smaller than that of the two source/drain implantation regions.

Abstract translation: 提供了制造多晶硅薄膜晶体管的方法。 该方法包括形成多晶硅有源层，顺序地在有源层上形成第一栅极绝缘层和第一栅电极，通过使用第一栅电极作为掩模在有源层上进行第一离子注入工艺以形成两个掺杂区域 在有源层的端部，顺序地在第一栅极绝缘层和第一栅电极上形成第二栅极绝缘层和第二栅电极，并且通过使用第二栅电极作为另一栅电极在有源层上进行第二离子注入工艺 掩模以在有源层的掺杂区域的两个外侧形成两个源极/漏极注入区域。 因此，两个掺杂区域的杂质浓度小于两个源极/漏极注入区域的杂质浓度。