公开(公告)号：US07937675B2

公开(公告)日：2011-05-03

申请号：US11935612

申请日：2007-11-06

申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, Jr. ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, Jr. ,  Edward J. Nowak

IPC分类号： G06F17/50 ,  H01L29/76

CPC分类号： H01L29/78615

摘要： A design structure including a transistor having a directly contacting gate and body is disclosed. In one embodiment, the transistor includes a gate; a body; and a dielectric layer extending over the body to insulate the gate from the body along an entire surface of the body except along a portion of at least a sidewall of the body, wherein the gate is in direct contact with the body at the portion.

摘要翻译： 公开了一种包括具有直接接触的栅极和主体的晶体管的设计结构。 在一个实施例中，晶体管包括栅极; 身体; 以及电介质层，其延伸到所述主体上，以沿着所述主体的至少一个侧壁的一部分沿着所述主体的整个表面使所述门与所述主体绝缘，其中所述门在所述部分处与所述主体直接接触。

公开(公告)号：US07910418B2

公开(公告)日：2011-03-22

申请号：US12022292

申请日：2008-01-30

申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, Jr. ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, Jr. ,  Edward J. Nowak

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/823842 ,  H01L21/76895 ,  H01L21/823871

摘要： Complementary metal gate dense interconnects and methods of manufacturing the interconnects is provided. The method comprises forming a first metal gate on a wafer and second metal gate on the wafer. A conductive interconnect material is deposited in a space formed between the first metal gate and the second metal gate to provide an electrical connection between the first metal gate and the second metal gate.

摘要翻译： 提供互补金属栅极致密互连和制造互连的方法。 该方法包括在晶片上形成第一金属栅极和在晶片上形成第二金属栅极。 导电互连材料沉积在形成在第一金属栅极和第二金属栅极之间的空间中，以在第一金属栅极和第二金属栅极之间提供电连接。

公开(公告)号：US07816738B2

公开(公告)日：2010-10-19

申请号：US11164651

申请日：2005-11-30

申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, Jr. ,  Jeffrey P. Gambino ,  Shih-Fen Huang ,  Edward J. Nowak ,  Anthony K. Stamper

发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, Jr. ,  Jeffrey P. Gambino ,  Shih-Fen Huang ,  Edward J. Nowak ,  Anthony K. Stamper

IPC分类号： H01L27/088

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78

摘要： In order to reduce power dissipation requirements, obtain full potential transistor performance and avoid power dissipation limitations on transistor performance in high density integrated circuits, transistors are operated in a sub-threshold (sub-Vth) or a near sub-Vth voltage regime (generally about 0.2 volts rather than a super-Vth regime of about 1.2 volts or higher) and optimized for such operation, particularly through simplification of the transistor structure, since intrinsic channel resistance is dominant in sub-Vth operating voltage regimes. Such simplifications include an underlap or recess of the source and drain regions from the gate which avoids overlap capacitance to partially recover loss of switching speed otherwise caused by low voltage operation, an ultra-thin gate structure having a thickness of 500 Å or less which also simplifies forming connections to the transistor and an avoidance of silicidation or alloy formation in the source, drain and/or gate of transistors.

摘要翻译： 为了降低功耗要求，获得全电位晶体管性能，并避免在高密度集成电路中对晶体管性能的功耗限制，晶体管工作在亚阈值（sub-Vth）或接近sub-Vth电压方式 约0.2伏，而不是约1.2伏特或更高的超电压状态），并且为了这种操作而进行了优化，特别是通过简化晶体管结构，因为在Vth的工作电压方案中固有的沟道电阻是主要的。 这种简化包括来自栅极的源极和漏极区域的欠叠或凹陷，其避免重叠电容以部分恢复由低电压操作引起的切换速度的损失，厚度为或等于或小于500埃的超薄栅极结构 简化了与晶体管的形成连接，避免了晶体管的源极，漏极和/或栅极中的硅化或合金形成。

公开(公告)号：US07741672B2

公开(公告)日：2010-06-22

申请号：US11933571

申请日：2007-11-01

申请人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

IPC分类号： H01L29/94 ,  H01L21/20

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： In a fin-type field effect transistor (FinFET) structure, a gate strap is positioned on the top of a gate conductor and runs along the gate conductor. The top of the gate strap is positioned a greater height above the top surface of the substrate than the top of the fin cap. The gate strap is conformal and, therefore, the top of the portion of the gate strap that crosses the fin cap has a greater height above the top surface of the substrate than top portions of other regions of the gate strap. Further, the material of the gate strap can have a different work function than a material of the gate conductor.

摘要翻译： 在鳍式场效应晶体管（FinFET）结构中，栅极带位于栅极导体的顶部并且沿着栅极导体延伸。 栅极带的顶部位于比衬垫顶部更高的高度，高于鳍帽的顶部。 栅极带是共形的，因此，跨过鳍片盖的栅极带的部分的顶部在栅极表面的其它区域的顶部之上具有比基板顶表面更高的高度。 此外，栅极带的材料可以具有与栅极导体的材料不同的功函数。

公开(公告)号：US20090319973A1

公开(公告)日：2009-12-24

申请号：US12144004

申请日：2008-06-23

申请人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak ,  Jed H. Rankin

发明人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak ,  Jed H. Rankin

IPC分类号： G06F17/50 ,  H01L21/00

CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： A design structure is provided for spacer fill structures and, more particularly, spacer fill structures, a method of manufacturing and a design structure for reducing device variation is provided. The structure includes a plurality of dummy fill shapes in different areas of a device which are configured such that gate perimeter to gate area ratio will result in a total perimeter density being uniform across a chip.

摘要翻译： 提供了用于间隔物填充结构的设计结构，并且更具体地，提供了间隔件填充结构，制造方法和用于减小装置变化的设计结构。 该结构包括在器件的不同区域中的多个虚拟填充形状，其被配置为使得栅极周边与栅极面积比将导致芯片上的总周长密度是均匀的。

公开(公告)号：US20090267156A1

公开(公告)日：2009-10-29

申请号：US12111285

申请日：2008-04-29

申请人： Brent A. Anderson ,  Andres Bryant ,  Josephine B. Chang ,  Michael A. Guillorn ,  Ryoji Hasumi ,  Edward J. Nowak ,  Mickey H. Yu

发明人： Brent A. Anderson ,  Andres Bryant ,  Josephine B. Chang ,  Michael A. Guillorn ,  Ryoji Hasumi ,  Edward J. Nowak ,  Mickey H. Yu

IPC分类号： H01L27/092 ,  G06F17/50

CPC分类号： H01L21/823481 ,  H01L27/1104

摘要： Device structures and design structures for a static random access memory. The device structure includes a well of a first conductivity type in a semiconductor layer, first and second deep trench isolation regions in the semiconductor layer that laterally bound a device region in the well, and first and second pluralities of doped regions of a second conductivity type in the first device region. A shallow trench isolation region extends laterally across in the device region to connect the first and second deep trench isolation regions, and is disposed in the device region between the first and second pluralities of doped regions. The shallow trench isolation region extends from the top surface into the semiconductor layer to a first depth such that the well is continuous beneath the shallow trench isolation region. A gate stack controls carrier flow between a pair of the first plurality of doped regions.

摘要翻译： 静态随机存取存储器的器件结构和设计结构。 器件结构包括在半导体层中的第一导电类型的阱，半导体层中的横向地限定阱中的器件区域的第一和第二深沟槽隔离区以及第二和第二多个第二导电类型的掺杂区 在第一个设备区域。 浅沟槽隔离区域在器件区域中横向延伸以连接第一和第二深沟槽隔离区域，并且设置在第一和第二多个掺杂区域之间的器件区域中。 浅沟槽隔离区域从顶表面延伸到半导体层到第一深度，使得阱在浅沟槽隔离区域下连续。 栅极堆叠控制一对第一多个掺杂区域之间的载流子流动。

公开(公告)号：US20090261425A1

公开(公告)日：2009-10-22

申请号：US12106476

申请日：2008-04-21

申请人： Brent A. Anderson ,  Andres Bryant ,  Josephine B. Chang ,  Omer H. Dokumaci ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  Josephine B. Chang ,  Omer H. Dokumaci ,  Edward J. Nowak

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/84

CPC分类号： H01L21/26513 ,  H01L21/26586 ,  H01L29/66803 ,  H01L29/785

摘要： A method patterns pairs of semiconducting fins on an insulator layer and then patterns a linear gate conductor structure over and perpendicular to the fins. Next, the method patterns a mask on the insulator layer adjacent the fins such that sidewalls of the mask are parallel to the fins and are spaced from the fins a predetermined distance. The method performs an angled impurity implant into regions of the fins not protected by the gate conductor structure and the mask. This process forms impurity concentrations within the fins that are asymmetric and that mirror one another in adjacent pairs of fins.

摘要翻译： 一种方法在绝缘体层上形成一对半导体翅片，然后在鳍片上并垂直于翅片形成线性栅极导体结构。 接下来，该方法在与鳍片相邻的绝缘体层上形成掩模，使得掩模的侧壁平行于翅片并与翅片间隔预定距离。 该方法对未被栅极导体结构和掩模保护的鳍片的区域进行倾斜的杂质注入。 该方法在翅片内形成不对称的杂质浓度，并且在相邻的翅片对中彼此相互镜像。

公开(公告)号：US07494850B2

公开(公告)日：2009-02-24

申请号：US11276135

申请日：2006-02-15

申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, Jr. ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, Jr. ,  Edward J. Nowak

IPC分类号： H01L21/20 ,  H01L29/06

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/11

摘要： Disclosed are embodiments of a structure that comprises a first device, having multiple FETs, and a second device, having at least one FET. Sections of a first portion of a semiconductor layer below the first device are doped and contacted to form back gates. A second portion of the semiconductor layer below the second device remains un-doped and un-contacted and, thus, functions as an insulator. Despite the performance degradation of the first device due to back gate capacitance, the back gates result in a net gain for devices such as, SRAM cells, which require precise Vt control. Contrarily, despite marginal Vt control in the second device due to the absence of back gates, the lack of capacitance loading and the added insulation result in a net gain for high performance devices such as, logic circuits.

摘要翻译： 公开了包括具有多个FET的第一器件和具有至少一个FET的第二器件的结构的实施例。 第一器件下方的半导体层的第一部分的部分被掺杂并接触以形成后栅极。 第二器件下方的半导体层的第二部分保持未掺杂和未接触，并因此用作绝缘体。 尽管由于背栅电容而导致第一器件的性能下降，但是后栅导致需要精确Vt控制的诸如SRAM单元的器件的净增益。 相反，尽管由于不存在后门而导致第二器件中的边缘Vt控制，但由于缺少电容负载和增加的绝缘，导致高性能器件（如逻辑电路）的净增益。

公开(公告)号：US20090020819A1

公开(公告)日：2009-01-22

申请号：US11778217

申请日：2007-07-16

申请人： Brent A. Anderson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Edward J. Nowak

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

摘要： Disclosed herein are embodiments of a multiple fin fin-type field effect transistor (i.e., a multiple fin dual-gate or tri-gate field effect transistor) in which the multiple fins are partially or completely merged by a highly conductive material (e.g., a metal silicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions. Merging the semiconductor fins in this manner also allows each of the source/drain regions to be contacted by a single contact via as well as more flexible placement of that contact via.

摘要翻译： 这里公开了多鳍片式场效应晶体管（即，多鳍式双栅极或三栅极场效应晶体管）的实施例，其中多个散热片部分或完全由高导电材料（例如， 金属硅化物）。 以这种方式合并散热片使串联电阻最小化，栅极和源极/漏极区之间的寄生电容几乎不增加。 以这种方式合并半导体散热片也允许每个源极/漏极区域通过单个触点通孔接触，以及该触点通孔的更灵活的放置。

公开(公告)号：US07473605B2

公开(公告)日：2009-01-06

申请号：US11866435

申请日：2007-10-03

申请人： Brent A. Anderson ,  Andres Bryant ,  Jeffrey B. Johnson ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  Jeffrey B. Johnson ,  Edward J. Nowak

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795

摘要： Disclosed are embodiments of a trigate field effect transistor that comprises a fin-shaped semiconductor body with a channel region and source/drain regions on either side of the channel region. Thick gate dielectric layers separate the top surface and opposing sidewalls of the channel region from the gate conductor in order to suppress conductivity in the channel planes. A thin gate dielectric layer separates the upper corners of the channel region from the gate conductor in order to optimize conductivity in the channel corners. To further emphasize the current flow in the channel corners, the source/drain regions can be formed in the upper corners of the semiconductor body alone. Alternatively, source/drain extension regions can be formed only in the upper corners of the semiconductor body adjacent to the gate conductor and deep source/drain diffusion regions can be formed in the ends of the semiconductor body.

摘要翻译： 公开了一种触发场效应晶体管的实施例，其包括具有沟道区的鳍状半导体本体和沟道区两侧的源极/漏极区。 厚栅电介质层将沟道区的顶表面和相对的侧壁与栅极导体分开，以便抑制沟道平面中的导电性。 薄栅极电介质层将沟道区的上角与栅极导体分开，以便优化沟道角中的导电性。 为了进一步强调通道角中的电流流动，源极/漏极区域可以单独形成在半导体主体的上角部。 或者，源极/漏极延伸区域仅可以形成在与栅极导体相邻的半导体本体的上角处，并且可以在半导体本体的端部形成深的源极/漏极扩散区域。