公开(公告)号：US20060195558A1

公开(公告)日：2006-08-31

申请号：US11066024

申请日：2005-02-25

申请人： Kevin Egan ,  Brad Underwood ,  Mark Shaw ,  Mark Shaw ,  Brian Johnson ,  D. Edwards

发明人： Kevin Egan ,  Brad Underwood ,  Mark Shaw ,  Mark Shaw ,  Brian Johnson ,  D. Edwards

IPC分类号： G06F15/173

CPC分类号： G06F15/16

摘要： A system comprises plural electronic modules, at least one interconnect structure and plural power supplies. The electronic modules communicate over the interconnect structure. The system further comprises plural redundant manager modules to perform management tasks with respect to the at least one interconnect structure and the power supplies.

摘要翻译： 一种系统包括多个电子模块，至少一个互连结构和多个电源。 电子模块通过互连结构进行通信。 该系统还包括多个冗余管理器模块，用于执行关于至少一个互连结构和电源的管理任务。

公开(公告)号：US20060184376A1

公开(公告)日：2006-08-17

申请号：US11065071

申请日：2005-02-25

申请人： Alan Graves ,  Jeff Fitchett ,  Brian Johnson ,  Brian Vezza ,  Guy Duxbury ,  Peter Ashwood-Smith

发明人： Alan Graves ,  Jeff Fitchett ,  Brian Johnson ,  Brian Vezza ,  Guy Duxbury ,  Peter Ashwood-Smith

IPC分类号： G06Q99/00

CPC分类号： G06Q50/22 ,  G06Q10/087 ,  G06Q50/265 ,  G08B13/2462 ,  G08B21/22 ,  Y02A90/22

摘要： A system for detecting potentially suspicious motion of a piece of equipment in a healthcare establishment. The system comprises a first functional entity adapted to determine a set of authorized clinicians associated with the piece of equipment; a second functional entity adapted to determine, based at least in part on data regarding wirelessly detectable tags associated with the authorized clinicians and the piece of equipment, when the piece of equipment is in motion and satisfies a remoteness condition with respect to a subset of the authorized clinicians; and a third functional entity adapted to signal potentially suspicious motion of the piece of equipment in response to the piece of equipment being in motion and satisfying the remoteness condition with respect to the subset of the authorized clinicians. In this way, it may be possible to thwart an attempted theft of equipment.

摘要翻译： 一种用于检测医疗保健机构中的一件设备的潜在可疑运动的系统。 该系统包括适于确定与该设备相关联的一组经授权的临床医师的第一功能实体; 第二功能实体至少部分地基于关于与所授权的临床医生和设备件相关联的无线可检测标签的数据，当该设备运动并且满足相对于所述设备的子集的远程条件时， 授权临床医生; 以及第三功能实体，其适于响应于所述设备运动而对所述设备的潜在可疑运动进行信号，并且相对于所授权的临床医生的子集满足所述远程状态。 以这种方式，可能会挫败企图盗窃设备。

公开(公告)号：US20060179430A1

公开(公告)日：2006-08-10

申请号：US11281906

申请日：2005-11-18

申请人： David Besbris ,  Brian Johnson ,  John Robinson ,  Donald Eaves ,  Xiaopeng Zhang

发明人： David Besbris ,  Brian Johnson ,  John Robinson ,  Donald Eaves ,  Xiaopeng Zhang

IPC分类号： G06F9/44 ,  G06F9/45

CPC分类号： G06F9/485 ,  G06F8/65 ,  G06F8/658 ,  G06F9/445 ,  G06F9/44536 ,  G06F9/465 ,  G06F9/5055 ,  G06F9/541 ,  G06F9/545 ,  G06F2209/462 ,  H04L51/00 ,  H04L51/04 ,  H04L67/16 ,  H04L69/24

摘要： A code module is loaded in-process or out-of-process depending on metadata. The code module implements a service and the metadata is associated with the service. The metadata also indicates whether the code module is to be loaded in-process or out-of-process. A request for a service object provided by the service is received from a service requestor. The metadata is examined to determine whether the code module is to be loaded in-process or out-of-process and, when the metadata indicates the code module is to be loaded in-process, the code module is loaded into the process of the service requester. When the metadata indicates the code module is to be loaded out-of-process, the code module is loaded into a host process separate from the process of the service requester. The requested service object is instantiated using the loaded code module and the service requestor is enabled to access the instantiated service object.

摘要翻译： 根据元数据，代码模块在进程内或进程外加载。 代码模块实现服务，元数据与服务相关联。 元数据还指示代码模块是要在进程中还是进程外加载。 从服务请求者接收到由服务提供的服务对象的请求。 检查元数据以确定代码模块是要在进程中还是进程外加载，并且当元数据指示要在进程中加载​​代码模块时，代码模块被加载到 服务请求者 当元数据表示代码模块被加载到进程外时，代码模块被加载到与服务请求者的进程分离的主机进程中。 所请求的服务对象使用加载的代码模块进行实例化，并且服务请求者被启用以访问实例化的服务对象。

公开(公告)号：US20060146600A1

公开(公告)日：2006-07-06

申请号：US11029981

申请日：2005-01-05

申请人： Brian Johnson

发明人： Brian Johnson

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C13/0033 ,  G11C13/0069 ,  G11C29/02 ,  G11C29/028 ,  G11C29/12005 ,  G11C2013/0092

摘要： Read disturbs in phase change memories may be reduced by progressively reducing the read pulse falling edges. This may reduce the possibility of quenching and inadvertent amorphization of at least a portion of the bit. As a result, in some embodiments, read disturbs may be reduced.

摘要翻译： 可以通过逐渐减小读取脉冲下降沿来减少相变存储器中的读取干扰。 这可能会降低钻头的至少一部分淬火和无意的非晶化的可能性。 结果，在一些实施例中，可以减少读取干扰。

公开(公告)号：US07057967B2

公开(公告)日：2006-06-06

申请号：US11001231

申请日：2004-12-01

申请人： Brian Johnson ,  Brent Keeth ,  Jeffrey W. Janzen ,  Troy A. Manning ,  Chris G. Martin

发明人： Brian Johnson ,  Brent Keeth ,  Jeffrey W. Janzen ,  Troy A. Manning ,  Chris G. Martin

IPC分类号： G11C8/00

CPC分类号： G11C29/12015 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C29/14

摘要： A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input signals, and a plurality of asynchronous input terminals for receiving a plurality of asynchronous input signals. The device further has a clock input for receiving an external clock signal thereon, with the device being specified by the manufacturer to be operated in the normal mode using an external clock signal having a frequency no less than a predetermined minimum frequency. An internal delay locked loop (DLL) clocking circuit is coupled to the clock input terminal and is responsive in normal operating mode to be responsive to the external clock signal to generate at least one internal clock signal. control circuitry in the device is responsive to a predetermined sequence of asynchronous signals applied to the device's asynchronous input terminals to place the device in an alternative mode of operation in which the internal clocking circuit is disabled, such that the device may be operated in the alternative mode using an external clock signal having a frequency less than the predetermined minimum frequency. The alternative mode of operation facilitates testing of the device at a speed less than the minimum frequency specified for the normal mode of operation.

摘要翻译： 同步半导体存储器件可以在正常模式和替代模式下操作。 半导体器件具有用于接收多个同步捕获的输入信号的命令总线和用于接收多个异步输入信号的多个异步输入端子。 该装置还具有用于在其上接收外部时钟信号的时钟输入，该装置由制造商指定为使用具有不小于预定最小频率的频率的外部时钟信号在正常模式下操作。 内部延迟锁定环（DLL）时钟电路耦合到时钟输入端并且在正常操作模式下响应于外部时钟信号响应以产生至少一个内部时钟信号。 设备中的控制电路响应于施加到设备的异步输入端子的预定的异步信号序列，以将设备置于其中内部时钟电路被禁用的替代操作模式，使得该设备可以以替代方式操作 模式使用具有小于预定最小频率的频率的外部时钟信号。 替代的操作模式便于以低于为正常操作模式指定的最小频率的速度测试设备。

公开(公告)号：US07038966B2

公开(公告)日：2006-05-02

申请号：US11030844

申请日：2005-01-07

申请人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

发明人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

IPC分类号： G11C7/00

CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

摘要： A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

公开(公告)号：US20060082478A1

公开(公告)日：2006-04-20

申请号：US11284498

申请日：2005-11-21

申请人： Brent Keeth ,  Brian Johnson ,  Troy Manning

发明人： Brent Keeth ,  Brian Johnson ,  Troy Manning

IPC分类号： H03M9/00

CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

摘要： A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

公开(公告)号：US20060054751A1

公开(公告)日：2006-03-16

申请号：US10941231

申请日：2004-09-15

申请人： Brian Johnson ,  Gary Coonan

发明人： Brian Johnson ,  Gary Coonan

IPC分类号： A47F5/00

CPC分类号： F16M11/24 ,  A47B9/00 ,  F16M11/2021 ,  F16M11/2092 ,  F16M11/38 ,  F16M11/42 ,  F16M13/00 ,  F16M2200/024 ,  F16M2200/044 ,  F16M2200/063

摘要： Mobile computer workstations must be sufficiently large in order to be stable, but small enough to be easily maneuverable through a work place. A vertically-adjustable mobile computer workstation of the present disclosure includes a pole rotatably attached to a base supported by a plurality of rotatable members. The pole includes a first arm rotatably attached to a second arm. A computer support is attached to the second arm and is moveable between a sitting user position and a standing user position, at least in part, by pivoting the arms of the pole with respect to one another and the moveable base.

摘要翻译： 移动计算机工作站必须足够大以便稳定，但足够小以便通过工作场所容易操纵。 本公开的可垂直调节的移动计算机工作站包括可旋转地附接到由多个可旋转构件支撑的基座的杆。 杆包括可旋转地附接到第二臂的第一臂。 计算机支撑件附接到第二臂，并且可以在坐使用者位置和站立的使用者位置之间移动，至少部分地通过相对于彼此和可移动的基座枢转杆的臂。

公开(公告)号：US20050263590A1

公开(公告)日：2005-12-01

申请号：US11049921

申请日：2005-02-03

申请人： James Branck ,  Brian Johnson

发明人： James Branck ,  Brian Johnson

IPC分类号： G06K15/00 ,  G07G1/00

CPC分类号： G07G1/0018

摘要： The present invention provides an integrated point of sale transaction terminal that includes both operator and customer interfaces. A housing for the electronics of the point of sale terminal comprises an operator interface unit integrally associated therewith and extending from one side thereof and a customer interface unit integrally associated therewith and extending from the opposing side thereof.

摘要翻译： 本发明提供了包括操作者和客户界面的综合销售点交易终端。 用于销售点终端的电子设备的壳体包括与其一体地相关联并从其一侧延伸的操作者接口单元和与其整体相关联并从其相对侧延伸的顾客接口单元。

公开(公告)号：US06965249B2

公开(公告)日：2005-11-15

申请号：US10159581

申请日：2002-05-30

申请人： Christopher Lane ,  Ketan Zaveri ,  Hyun Yi ,  Giles Powell ,  Paul Leventis ,  David Jefferson ,  David Lewis ,  Triet Nguyen ,  Vikram Santurkar ,  Michael Chan ,  Andy Lee ,  Brian Johnson ,  David Cashman

发明人： Christopher Lane ,  Ketan Zaveri ,  Hyun Yi ,  Giles Powell ,  Paul Leventis ,  David Jefferson ,  David Lewis ,  Triet Nguyen ,  Vikram Santurkar ,  Michael Chan ,  Andy Lee ,  Brian Johnson ,  David Cashman

IPC分类号： H01L21/82 ,  H03K19/177

CPC分类号： H03K19/17764 ,  H03K19/17736 ,  H03K19/17744

摘要： A programmable logic device and associated method is provided with repairable regions. In one aspect, general routing interconnect lines are segmented within repairable regions. In another aspect, IO bus lines and associated circuitry are provided that accommodate redundancy in a staggered segmented architecture. In another aspect, a dedicated routing architecture between particular logic regions accommodates shifting to define and utilize repairable regions. Principles of other aspects are illustrated and described in the context of several exemplary embodiments of aspects of the invention.

摘要翻译： 可编程逻辑器件和相关方法提供有可修复区域。 在一个方面，一般布线互连线在可修复区域内被分段。 在另一方面，提供IO总线线路和相关电路，其适应交错分段结构中的冗余。 在另一方面，特定逻辑区域之间的专用路由架构适应移位以限定和利用可修复区域。 在本发明的方面的几个示例性实施例的上下文中示出和描述了其它方面的原理。