公开(公告)号：US06566250B1

公开(公告)日：2003-05-20

申请号：US10100429

申请日：2002-03-18

申请人： Yeur-Luen Tu ,  Chih-Yang Pai ,  Chia-Shiung Tsai

发明人： Yeur-Luen Tu ,  Chih-Yang Pai ,  Chia-Shiung Tsai

IPC分类号： H01L214763

CPC分类号： H01L21/76843 ,  H01L21/288 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76873

摘要： A method for forming a self-aligned capping layer over a metal filled feature in a multi-layer semiconductor device including providing an anisotropically etched feature included in a substrate; blanket depositing a first barrier layer over the anisotropically etched feature to prevent diffusion of a metal species into the substrate; filling the anisotropically etched feature with a metal to form a metal filled feature substantially filled with metal; planarizing the substrate surface to include forming an exposed surface of the metal filled feature; and, selectively depositing a second barrier layer to cover the exposed surface of the metal filled feature to form a capping layer.

摘要翻译： 一种用于在多层半导体器件中的金属填充特征上形成自对准覆盖层的方法，包括提供包括在衬底中的各向异性蚀刻特征; 在各向异性蚀刻的特征上毯覆盖沉积第一阻挡层以防止金属物质扩散到基底中; 用金属填充各向异性蚀刻的特征以形成充满金属的金属填充特征; 平面化基底表面以包括形成填充金属的特征的暴露表面; 以及选择性地沉积第二阻挡层以覆盖所述金属填充特征的暴露表面以形成覆盖层。

公开(公告)号：US06501120B1

公开(公告)日：2002-12-31

申请号：US10053151

申请日：2002-01-15

申请人： Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Min-Hwa Chi

发明人： Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Min-Hwa Chi

IPC分类号： H01L218242

CPC分类号： H01L27/10888 ,  H01L21/7682 ,  H01L27/10811 ,  H01L28/84 ,  H01L28/90

摘要： Within both: (1) a method for forming a memory cell structure within a semiconductor integrated circuit microelectronic fabrication; and (2) the memory cell structure resulting from the method, there is provided a capacitor structure whose sidewall is separated from a bitline stud layer which is adjacent thereto and extends there above, by an air gap void. The air gap void provides for attenuated bitline to capacitor structure capacitive coupling, and thus enhanced performance of the memory cell structure.

摘要翻译： 在两者中：（1）在半导体集成电路微电子制造中形成存储单元结构的方法; 和（2）由该方法得到的存储单元结构，提供了一个电容器结构，其电容器结构的侧壁与位于其周围的位线柱层分离，并在其上方延伸有气隙空隙。 气隙空隙为衰减位线提供电容结构电容耦合，从而提高存储单元结构的性能。

公开(公告)号：US06383943B1

公开(公告)日：2002-05-07

申请号：US09687160

申请日：2000-10-16

申请人： Chao-Cheng Chen ,  Jen-Cheng Liu ,  Jyu-Horng Shieh ,  Chia-Shiung Tsai ,  Bor-Shyang Lin

发明人： Chao-Cheng Chen ,  Jen-Cheng Liu ,  Jyu-Horng Shieh ,  Chia-Shiung Tsai ,  Bor-Shyang Lin

IPC分类号： H01L21302

CPC分类号： H01L21/76843 ,  H01L21/3105 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76829

摘要： A method for eliminating the problems associated with the discontinuous deposition of the glue layer at the bottom of the via resulting from the notch in the silicon nitride etch stop layer. First conductive layer traces are patterned and a silicon nitride (SiN) etch stop layer is provided overlying the first conductive layer. An inter-metal dielectric (IMD) layer then overlies the entire surface. An anisotropic etch is performed leaving via holes in the IMD layer. This is followed by a second anisotropic etch step to remove the etch stop layer not protected by the IMD layer resulting in the formation a notch at the bottom of the via hole. An important step of the present invention is the elimination of this notch accomplished by nitridizing the surface of the IMD layer. A wet polymer cleaning is performed to remove the nitridized IMD surface and eliminating the notch. A glue layer is conformally applied lining the via hole. A second conductive layer is then deposited and the surface is planarized.

摘要翻译： 一种用于消除与在氮化硅蚀刻停止层中由凹口产生的通孔底部的胶层不连续沉积相关的问题的方法。 图案化第一导电层迹线，并且覆盖第一导电层提供氮化硅（SiN）蚀刻停止层。 金属间电介质（IMD）层然后覆盖整个表面。 进行各向异性蚀刻，留下IMD层中的通孔。 然后进行第二个各向异性蚀刻步骤以去除不被IMD层保护的蚀刻停止层，从而在通孔的底部形成切口。 本发明的重要步骤是消除通过使IMD层的表面氮化而实现的这个缺口。 执行湿式聚合物清洁以除去氮化的IMD表面并消除凹口。 粘合层适用于衬套通孔。 然后沉积第二导电层并且将表面平坦化。

公开(公告)号：US06271084B1

公开(公告)日：2001-08-07

申请号：US09759912

申请日：2001-01-16

申请人： Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Min-Hwa Chi

发明人： Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Min-Hwa Chi

IPC分类号： H01L218242

CPC分类号： H01L28/82 ,  H01L21/76838 ,  H01L21/76895 ,  H01L27/10855 ,  H01L27/10894 ,  H01L28/55 ,  H01L28/60

摘要： A process for forming a vertical, metal-insulator-metal (MIM), capacitor structure, for embedded DRAM devices, using a damascene procedure, has been developed. The process features forming a capacitor opening in a composite insulator layer comprised of a overlying insulator stop layer, a low k insulator layer, and an underlying insulator stop layer, with a lateral recess isotropically formed in the low k insulator layer. After formation of a bottom electrode structure in the capacitor opening, a high k insulator layer is deposited followed by the deposition of a conductive layer, completely filling the capacitor opening. A chemical mechanical polishing procedure is then used to remove portions of the conductive layer, and portions of the high k insulator layer, from the top surface of the overlying insulator stop layer, resulting in the formation of the vertical MIM capacitor structure, in the capacitor opening, comprised of: a top electrode structure, defined from the conductive layer; a capacitor dielectric layer, formed from the high k insulator layer; and a bottom electrode structure.

摘要翻译： 已经开发了使用镶嵌程序形成用于嵌入式DRAM器件的垂直金属 - 绝缘体金属（MIM），电容器结构的工艺。 该工艺的特征是在复合绝缘层中形成电容器开口，该复合绝缘层由上覆的绝缘体停止层，低k绝缘体层和下面的绝缘体阻挡层组成，在低k绝缘体层中各向同性地形成有横向凹槽。 在电容器开口中形成底部电极结构之后，沉积高k绝缘体层，随后沉积导电层，完全填充电容器开口。 然后使用化学机械抛光方法从上覆绝缘体停止层的顶表面去除导电层的部分和高k绝缘体层的部分，从而在电容器中形成垂直MIM电容器结构 开口，包括：由导电层限定的顶部电极结构; 由高k绝缘体层形成的电容器电介质层; 和底部电极结构。

公开(公告)号：US06242362B1

公开(公告)日：2001-06-05

申请号：US09366736

申请日：1999-08-04

申请人： Jen-Cheng Liu ,  Huan-Just Lin ,  Chia-Shiung Tsai ,  Yung-Kuan Hsaio

发明人： Jen-Cheng Liu ,  Huan-Just Lin ,  Chia-Shiung Tsai ,  Yung-Kuan Hsaio

IPC分类号： H01L21302

CPC分类号： H01L21/32137 ,  H01L21/32139

摘要： The present invention provides a method of fabricating a vertical hard mask/conductive pattern profile. The process begins by forming a polysilicon or more preferably a polysilicon and silicide conductive layer over a semiconductor substrate. A silicon oxynitride hard mask layer is formed over the conductive layer. The silicon oxynitride hard mask layer is patterned to form a hard mask pattern. The conductive layer is patterned to form a conductive pattern using Cl2/He—O2/N2 etch chemistry, thereby forming a hard mask/conductive pattern profile that is vertical.

摘要翻译： 本发明提供了制造垂直硬掩模/导电图案轮廓的方法。 该过程通过在半导体衬底上形成多晶硅或更优选多晶硅和硅化物导电层开始。 在导电层上形成氧氮化硅硬掩模层。 将氮氧化硅硬掩模层图案化以形成硬掩模图案。 使用Cl 2 / He-O 2 / N 2蚀刻化学法将导电层图案化以形成导电图案，从而形成垂直的硬掩模/导电图案轮廓。

公开(公告)号：US06225203B1

公开(公告)日：2001-05-01

申请号：US09304334

申请日：1999-05-03

申请人： Jen-Cheng Liu ,  Jen-Shiang Leu ,  Chia-Shiung Tsai

发明人： Jen-Cheng Liu ,  Jen-Shiang Leu ,  Chia-Shiung Tsai

IPC分类号： H01L21302

CPC分类号： H01L27/10855 ,  H01L21/31116 ,  H01L21/3185 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10885

摘要： A method of forming a PE-CVD silicon nitride spacer having a good profile in the fabrication of a self-aligned contact wherein a two-step etching process forms the spacer is described. Semiconductor device structures are formed on a semiconductor substrate. A layer of silicon nitride is deposited by plasma-enhanced chemical vapor deposition over the surface of the substrate and overlying the semiconductor device structures. The silicon nitride layer is etched away using a two-step etching process to leave silicon nitride spacers on the side surfaces of the semiconductor device structures. The two-step process comprises a first etching away of 70% of the silicon nitride layer using Cl2/He chemistry and a second etching away of the remaining silicon nitride on top surface of the semiconductor device strucutures using SF6/CHF3/He chemistry.

摘要翻译： 描述了在制造自对准接触中具有良好外形的PE-CVD氮化硅间隔物的方法，其中两步蚀刻工艺形成间隔物。 半导体器件结构形成在半导体衬底上。 通过等离子体增强化学气相沉积在衬底的表面上并覆盖半导体器件结构来沉积氮化硅层。 使用两步蚀刻工艺蚀刻掉氮化硅层，以在半导体器件结构的侧表面上留下氮化硅间隔物。 两步法包括使用Cl2 / He化学法首先蚀刻掉70％的氮化硅层，并且使用SF6 / CHF3 / He化学法在半导体器件结构的顶表面上第二次蚀刻剩余的氮化硅。

公开(公告)号：US5674775A

公开(公告)日：1997-10-07

申请号：US803466

申请日：1997-02-20

申请人： Chin-Hsiung Ho ,  Chia-Shiung Tsai ,  Cheng-Kai Liu ,  Chaochieh Tsai

发明人： Chin-Hsiung Ho ,  Chia-Shiung Tsai ,  Cheng-Kai Liu ,  Chaochieh Tsai

IPC分类号： H01L21/308 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76232 ,  H01L21/3086 ,  Y10S148/05

摘要： The present invention provides a method of manufacturing a trench having rounded top corners 28 in a substrate. The rounded top edges allow the formation of a gate oxide with a uniform thickness around the trench thereby reducing parasitic field FET problems. The method begins by forming a pad layer 14 over a semiconductor substrate 10. Next, an insulating layer 18 composed of silicon nitride is formed over the pad layer 14. A first opening 19 is formed in the insulating layer 18 and the pad layer 14 exposing the surface of the substrate. The first opening is defined by sidewalls of the pad layer 14 and of the insulating layer 18. An etch buffer layer 20 composed of polysilicon is formed over the resultant surface. In one etch step, the etch buffer layer 20 is anisotropically etched forming spacers 22 on the sidewalls of the pad layer 14 and of the insulating layer 18. The same etch step continues by etching the spacers 22 and the exposed substrate in the first opening 19 thereby forming a trench 26 in the substrate 10. Because the etch has to etch through the spacers before it reached the substrate, the trench 26 has rounded top edges 28 near the pad layer 14. Lastly, the pad layer 14 and the first insulating layer 18 are removed thereby forming the trench 26 with rounded top edges 28.

摘要翻译： 本发明提供一种制造在衬底中具有圆形顶角28的沟槽的方法。 圆形顶部边缘允许在沟槽周围形成均匀厚度的栅极氧化物，从而减少寄生场FET问题。 该方法开始于在半导体衬底10上形成衬垫层14.接下来，在衬底层14上形成由氮化硅构成的绝缘层18.第一开口19形成在绝缘层18中，衬垫层14暴露 衬底的表面。 第一开口由衬垫层14和绝缘层18的侧壁限定。在所得表面上形成由多晶硅构成的蚀刻缓冲层20。 在一个蚀刻步骤中，蚀刻缓冲层20被各向异性蚀刻，在衬垫层14和绝缘层18的侧壁上形成间隔物22.通过在第一开口19中蚀刻间隔物22和暴露的衬底，继续相同的蚀刻步骤 从而在衬底10中形成沟槽26.因为蚀刻必须在其到达衬底之前蚀刻穿过间隔物，所以沟槽26在焊盘层14附​​近具有圆形的顶部边缘28.最后，焊盘层14和第一绝缘层 18被去除，从而形成具有圆形顶部边缘28的沟槽26。

公开(公告)号：US09123671B2

公开(公告)日：2015-09-01

申请号：US12982275

申请日：2010-12-30

申请人： Chi-Ming Chen ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Ho-Yung David Hwang ,  Alexander Kalnitsky

发明人： Chi-Ming Chen ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Ho-Yung David Hwang ,  Alexander Kalnitsky

IPC分类号： H01L21/322

CPC分类号： H01L21/3225

摘要： Provided is a method of fabricating a semiconductor device. The method includes: receiving a silicon wafer that contains oxygen; forming a zone in the silicon wafer, the zone being substantially depleted of oxygen; causing a nucleation process to take place in the silicon wafer to form oxygen nuclei in a region of the silicon wafer outside the zone; and growing the oxygen nuclei into defects. Also provided is an apparatus that includes a silicon wafer. The silicon wafer includes: a first portion that is substantially free of oxygen, the first portion being disposed near a surface of the silicon wafer; and a second portion that contains oxygen; wherein the second portion is at least partially surrounded by the first portion.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括：接收含有氧的硅晶片; 在硅晶片中形成区域，该区域基本上耗尽氧气; 导致在硅晶片中发生成核过程，以在区域外的硅晶片的区域中形成氧核; 并将氧原子生长成缺陷。 还提供了一种包括硅晶片的装置。 硅晶片包括：基本上不含氧的第一部分，第一部分设置在硅晶片的表面附近; 和含有氧的第二部分; 其中所述第二部分至少部分地被所述第一部分包围。

公开(公告)号：US08921959B2

公开(公告)日：2014-12-30

申请号：US13190966

申请日：2011-07-26

申请人： Fu-Ting Sung ,  Shih-Chang Liu ,  Chia-Shiung Tsai

发明人： Fu-Ting Sung ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L29/82 ,  G11C11/00 ,  H01L21/00 ,  H01L43/12 ,  H01L43/08

CPC分类号： H01L43/12 ,  H01L43/08

摘要： According to an embodiment, a magnetoresistive random access memory (MRAM) device comprises a bottom electrode, a stack, a dielectric material, a dielectric layer, and a conductive material. The bottom electrode is over a substrate, and the stack is over the bottom electrode. The stack comprises a magnetic tunnel junction (MTJ) and a top electrode. The dielectric material is along a sidewall of the stack, and the dielectric material has a height greater than a thickness of the MTJ and less than a stack height. The dielectric layer is over the stack and the dielectric material. The conductive material extends through the dielectric layer to the top electrode of the stack.

摘要翻译： 根据实施例，磁阻随机存取存储器（MRAM）器件包括底部电极，堆叠，电介质材料，电介质层和导电材料。 底部电极在衬底上方，并且堆叠层在底部电极之上。 堆叠包括磁性隧道结（MTJ）和顶部电极。 介电材料沿着堆叠的侧壁，并且电介质材料具有高于MTJ的厚度并小于堆叠高度的高度。 电介质层在电池堆和电介质材料之上。 导电材料通过电介质层延伸到堆叠的顶部电极。

公开(公告)号：US08889507B2

公开(公告)日：2014-11-18

申请号：US11765971

申请日：2007-06-20

申请人： Chih-Ta Wu ,  Jason Lee ,  Chung Chien Wang ,  Hsing-Lien Lin ,  Yu-Jen Wang ,  Yeur-Luen Tu ,  Chern-Yow Hsu ,  Yuan-Hung Liu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Lucy Chang ,  Chia-Lin Chen ,  Ming-Chih Tsai

发明人： Chih-Ta Wu ,  Jason Lee ,  Chung Chien Wang ,  Hsing-Lien Lin ,  Yu-Jen Wang ,  Yeur-Luen Tu ,  Chern-Yow Hsu ,  Yuan-Hung Liu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Lucy Chang ,  Chia-Lin Chen ,  Ming-Chih Tsai

IPC分类号： H01L21/8234 ,  H01L21/8244 ,  H01L49/02 ,  H01L27/108

CPC分类号： H01L27/10814 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/75

摘要： A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing environment to convert a top layer of the bottom electrode into a buffer layer; forming an insulating layer on the buffer layer; and forming a top electrode over the insulating layer.

摘要翻译： 提供电容器及其形成方法。 该方法包括形成底部电极; 在含氧环境中处理底部电极以将底部电极的顶层转化为缓冲层; 在缓冲层上形成绝缘层; 并在所述绝缘层上形成顶部电极。