公开(公告)号：US06258697B1

公开(公告)日：2001-07-10

申请号：US09502333

申请日：2000-02-11

申请人： Jayendra Bhakta ,  Paul Besser ,  Minh Van Ngo

发明人： Jayendra Bhakta ,  Paul Besser ,  Minh Van Ngo

IPC分类号： H01L2176

CPC分类号： H01L21/02164 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/31612 ,  H01L21/76224

摘要： A method for manufacturing a semiconductor device forms a trench of a trench isolation region in a portion of a top surface of a semiconductor substrate. Oxide is deposited as a trench liner in the trench using low pressure chemical vapor deposition (LPCVD) high temperature oxidation (HTO). As LPCVD is a stress neutral process, stress defects in an interface between the silicon substrate and the oxide layer are avoided, so that subsequent etching steps in a local interconnect process are less likely to overetch at the interface. This reduces the possibility of junction leakage when the local interconnect is formed.

摘要翻译： 半导体器件的制造方法在半导体衬底的顶表面的一部分中形成沟槽隔离区的沟槽。 使用低压化学气相沉积（LPCVD）高温氧化（HTO）将氧化物作为沟槽衬垫沉积在沟槽中。 由于LPCVD是应力中性过程，因此避免了硅衬底和氧化物层之间的界面中的应力缺陷，使得局部互连工艺中的后续蚀刻步骤不太可能在界面处过蚀刻。 当局部互连形成时，这减少了结漏电的可能性。

公开(公告)号：US06211084B1

公开(公告)日：2001-04-03

申请号：US09112161

申请日：1998-07-09

申请人： Minh Van Ngo ,  Shekhar Pramanick ,  Takeshi Nogami

发明人： Minh Van Ngo ,  Shekhar Pramanick ,  Takeshi Nogami

IPC分类号： H01L2144

CPC分类号： H01L21/76849 ,  H01L21/76834 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： The adhesion of a diffusion barrier or capping layer to Cu and/or Cu alloy interconnect members is significantly enhanced by treating the exposed surface of the Cu and/or Cu alloy interconnect members with a silane or dichlorosilane plasma to form a layer of copper silicide thereon prior to depositing the capping layer. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in a dielectric interlayer, chemical mechanical polishing, treating the exposed surface of the Cu or Cu alloy interconnect member in a silane or dichlorosilane plasma to form the copper silicide layer and depositing a capping layer of silicon nitride thereon.

摘要翻译： 通过用硅烷或二氯硅烷等离子体处理Cu和/或Cu合金互连构件的暴露表面以在其上形成硅化铜层，扩散阻挡层或覆盖层对Cu和/或Cu合金互连构件的粘附性显着增强 在沉积覆盖层之前。 实施例包括电镀或化学镀Cu或Cu合金以填充介电中间层中的镶嵌开口，化学机械抛光，处理硅烷或二氯硅烷等离子体中Cu或Cu合金互连构件的暴露表面以形成硅化铜层和 在其上沉积氮化硅覆盖层。

公开(公告)号：US6143672A

公开(公告)日：2000-11-07

申请号：US084442

申请日：1998-05-22

申请人： Minh Van Ngo ,  Simon S. Chan ,  Suzette K. Pangrle ,  Robert A. Huertas

发明人： Minh Van Ngo ,  Simon S. Chan ,  Suzette K. Pangrle ,  Robert A. Huertas

IPC分类号： C23C16/40 ,  H01L21/316 ,  H01L21/768 ,  H01L21/76 ,  H01L21/469

CPC分类号： H01L21/02164 ,  C23C16/402 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31608 ,  H01L21/76801

摘要： In one embodiment, the present invention relates to a method of depositing a dielectric layer over a stacked interconnect structure, involving the steps of: providing a substrate having at least one stacked interconnect structure comprising at least one of an aluminum layer and an aluminum alloy layer; depositing the dielectric layer over the stacked interconnect structureunder a pressure from about 1 mTorr to about 6 mTorr, an O.sub.2 flow rate from about 110 sccm to about 130 sccm and a silane flow rate from about 52 sccm to about 60 sccm at a bias power from about 2500 W to about 3100 W,under a pressure from about 2 Torr to about 2.8 Torr, an N.sub.2 flow rate from about 7 l to about 11.5 l, an N.sub.2 O flow rate from about 1 l to about 2 l and a silane flow rate from about 250 sccm to about 300 sccm at a power from about 900 W to about 1300 W at a temperature from about 300.degree. C. to about 350.degree. C., orunder a pressure from about 2 Torr to about 2.8 Torr, an N.sub.2 flow rate from about 7 l to about 11.5 l, an N.sub.2 O flow rate from about 1 l to about 2 l and a silane flow rate from about 80 sccm to about 120 sccm at a power from about 900 W to about 1300 W at a temperature from about 390.degree. C. to about 410.degree. C.

摘要翻译： 在一个实施例中，本发明涉及一种在堆叠的互连结构上沉积电介质层的方法，其包括以下步骤：提供具有至少一个堆叠互连结构的衬底，所述堆叠互连结构包括铝层和铝合金层中的至少一个 ; 在约1mTorr至约6mTorr的压力下，将电介质层沉积在堆叠的互连结构上，O 2流速为约110sccm至约130sccm，硅烷流速为约52sccm至约60sccm，偏置功率 约2500W至约3100W，在约2托至约2.8托的压力下，N 2流速为约7升至约11.5升，N 2 O流速为约1升至约2升，硅烷流量 在约300至约350℃的温度或约2托至约2.8托的压力下以约900至约1300瓦的功率从约250sccm至约300sccm的速率， N 2流速为约7升至约11.5升，N 2 O流速为约1升至约2升，硅烷流速为约80sccm至约120sccm，功率为约900W至约1300W， 温度约390℃至约410℃

公开(公告)号：US6140255A

公开(公告)日：2000-10-31

申请号：US261543

申请日：1999-03-03

申请人： Minh Van Ngo ,  Terri Jo Kitson ,  Khanh Nguyen

发明人： Minh Van Ngo ,  Terri Jo Kitson ,  Khanh Nguyen

IPC分类号： C23C16/40 ,  C23C16/509 ,  H01L21/033 ,  H01L21/316 ,  H01L21/31 ,  H01L21/469

CPC分类号： C23C16/402 ,  C23C16/5096 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0332 ,  H01L21/31612

摘要： A method for depositing silicon nitride on a semiconductor wafer uses plasma enhanced chemical vapor deposition at very low temperatures. The temperature in a silicon nitride deposition chamber is set to be about 170.degree. C. or less. Silane gas (SiH.sub.4) flows into the silicon nitride deposition chamber with a flow rate in a range of from about 300 sccm (standard cubic cm per minute) to about 500 sccm. Nitrogen gas (N.sub.2) flows into the silicon nitride deposition chamber with a flow rate in a range of from about 500 sccm to about 2000 sccm. Ammonia gas (NH.sub.3) flows into the silicon nitride deposition chamber with a flow rate in a range of from about 1.0 slm to about 2.2 slm. A high frequency RF signal is applied on a showerhead within the deposition chamber. A low frequency RF signal is applied on a heating block for holding the semiconductor wafer. A predetermined volume for the silicon nitride deposition chamber is used such that pressure within the silicon nitride deposition chamber is in a range of from about 1.0 torr to about 2.4 torr. The semiconductor wafer is placed inside the silicon nitride deposition chamber for a soak time period of about 30 seconds or greater before the high frequency RF signal is applied on the showerhead in the deposition chamber and the low frequency RF signal is applied on the heating block. When the semiconductor wafer reaches the deposition temperature, the high frequency RF signal and the low frequency RF signal are applied for deposition of the silicon nitride layer onto the semiconductor wafer. By using low temperatures during the deposition of the silicon nitride layer, the structural integrity of any structure already on the semiconductor wafer is advantageously preserved.

摘要翻译： 在半导体晶片上沉积氮化硅的方法在非常低的温度下使用等离子体增强化学气相沉积。 氮化硅沉积室中的温度设定为约170℃以下。 硅烷气体（SiH4）以约300sccm（标准立方厘米每分钟）的流速流入氮化硅沉积室至约500sccm。 氮气（N 2）以约500sccm至约2000sccm的流速流入氮化硅沉积室。 氨气（NH 3）以约1.0slm至约2.2slm的流速流入氮化硅沉积室。 高频RF信号施加在沉积室内的喷头上。 将低频RF信号施加在用于保持半导体晶片的加热块上。 使用用于氮化硅沉积室的预定体积，使得氮化硅沉积室内的压力在约1.0托至约2.4托的范围内。 将半导体晶片放置在氮化硅沉积室的内部，用于在沉积室内的喷头上施加高频RF信号之前约30秒或更长的浸泡时间，并且将低频RF信号施加到加热块上。 当半导体晶片达到沉积温度时，施加高频RF信号和低频RF信号以将氮化硅层沉积到半导体晶片上。 通过在沉积氮化硅层期间使用低温，有利地保留已经在半导体晶片上的任何结构的结构完整性。

公开(公告)号：US6127261A

公开(公告)日：2000-10-03

申请号：US559054

申请日：1995-11-16

申请人： Minh Van Ngo ,  Darin A. Chan

发明人： Minh Van Ngo ,  Darin A. Chan

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/316

CPC分类号： H01L21/76801 ,  H01L21/76829 ,  H01L23/5329 ,  H01L2924/0002

摘要： A method of depositing a premetal dielectric layer involves deposition of a triple premetal dielectric layer in in-situ deposition in a single fabrication tool with each subsequent layer being deposited after a previous layer with no intervening handling step. Thus, no intervening cleaning steps or other intermediate steps are performed.

摘要翻译： 沉积预金属介电层的方法包括在单一制造工具中原位沉积中沉积三重预金属介电层，其中每个后续层在先前层之后沉积，而不需要中间处理步骤。 因此，不执行介入的清洁步骤或其他中间步骤。

公开(公告)号：US6060404A

公开(公告)日：2000-05-09

申请号：US924130

申请日：1997-09-05

申请人： Minh Van Ngo ,  Darin A. Chan ,  Sey-Ping Sun ,  Terri Kitson ,  John Caffall

发明人： Minh Van Ngo ,  Darin A. Chan ,  Sey-Ping Sun ,  Terri Kitson ,  John Caffall

IPC分类号： H01L21/314 ,  H01L21/768 ,  H01L21/72

CPC分类号： H01L21/76801 ,  H01L21/3144 ,  H01L21/76834 ,  H01L21/76895

摘要： An in-situ deposition method allows for the forming of a dielectric layer suitable for use in forming a conductive path in a semiconductor wafer. The method includes depositing a thin SiO.sub.x N.sub.y stop layer on top of a semiconductor wafer within a chemical vapor deposition (CVD) reactor chamber having a low pressure, maintaining the low pressure following the deposition of the SiO.sub.x N.sub.y stop layer, and then depositing a thick TEOS oxide dielectric layer on the SiO.sub.x N.sub.y stop layer within the CVD reactor chamber. The in-situ deposition process reduces outgassing defects that would normally form at the interface between the SiON stop layer and the TEOS oxide dielectric layer.

摘要翻译： 原位沉积方法允许形成适合用于在半导体晶片中形成导电路径的电介质层。 该方法包括在具有低压的化学气相沉积（CVD）反应器室内的半导体晶片的顶部上沉积薄的SiOxNy阻挡层，保持在沉积SiO x N y终止层之后的低压，然后沉积厚的TEOS氧化物 在CVD反应器室内的SiOxNy停止层上的介电层。 原位沉积过程减少了通常在SiON阻挡层和TEOS氧化物介电层之间的界面处形成的除气缺陷。

公开(公告)号：US6051870A

公开(公告)日：2000-04-18

申请号：US992333

申请日：1997-12-17

申请人： Minh Van Ngo

发明人： Minh Van Ngo

IPC分类号： H01L21/316 ,  H01L21/8247 ,  H01L29/00

CPC分类号： H01L27/11521 ,  H01L21/02129 ,  H01L21/02274 ,  H01L21/31625

摘要： A semiconductor structure includes a substrate, a microelectronic device formed on the substrate, and a dielectric layer including silicon dioxide formed over the microelectronic device. The silicon dioxide layer is doped with phosphorous in the form of approximately 96% SiO.sub.2 and 4% phosphorous (PH.sub.3) by weight, and has high etch selectivity, polish rate and gettering capability as well as excellent step coverage. The present process also improves uniformity and process control because phosphine is a gas and does not have to be vaporized prior to deposition.

摘要翻译： 半导体结构包括衬底，形成在衬底上的微电子器件，以及包含形成在微电子器件上的二氧化硅的电介质层。 二氧化硅层以约96％SiO 2和4％磷（PH 3）的形式掺杂磷，并且具有高蚀刻选择性，抛光速率和吸杂能力以及优异的台阶覆盖。 本方法还改善均匀性和工艺控制，因为磷化氢是气体，并且在沉积之前不必蒸发。

公开(公告)号：US08658496B2

公开(公告)日：2014-02-25

申请号：US13617291

申请日：2012-09-14

申请人： Hiroyuki Kinoshita ,  Angela Hui ,  Hsiao-Han Thio ,  Kuo-Tung Chang ,  Minh Van Ngo ,  Hiroyuki Ogawa

发明人： Hiroyuki Kinoshita ,  Angela Hui ,  Hsiao-Han Thio ,  Kuo-Tung Chang ,  Minh Van Ngo ,  Hiroyuki Ogawa

IPC分类号： H01L21/336

CPC分类号： H01L21/0217 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/7881

摘要： A memory device and a method of making the memory device are provided. A first dielectric layer is formed on a substrate, a floating gate is formed on the first dielectric layer, a second dielectric layer is formed on the floating gate, a control gate is formed on the second dielectric layer, and at least one film, including a conformal film, is formed over a surface of the memory device.

摘要翻译： 提供存储器件和制造存储器件的方法。 在基板上形成第一电介质层，在第一电介质层上形成浮栅，在浮栅上形成第二电介质层，在第二电介质层上形成控制栅，还包括至少一层， 保形膜形成在存储器件的表面上。

公开(公告)号：US08564041B2

公开(公告)日：2013-10-22

申请号：US11551532

申请日：2006-10-20

申请人： Angela T. Hui ,  Wenmei Li ,  Minh Van Ngo ,  Amol Ramesh Joshi ,  Kuo-Tung Chang

发明人： Angela T. Hui ,  Wenmei Li ,  Minh Van Ngo ,  Amol Ramesh Joshi ,  Kuo-Tung Chang

IPC分类号： H01L27/108

CPC分类号： H01L29/78 ,  H01L27/115 ,  H01L27/11568

摘要： A memory device includes a number of memory cells and a dielectric layer formed over the memory cells. The memory device also includes contacts formed in the dielectric layer and spacers formed adjacent the side surfaces of the contacts. The spacers may inhibit leakage currents from the contacts.

摘要翻译： 存储器件包括多个存储单元和形成在存储单元上的电介质层。 存储器件还包括形成在电介质层中的触点和邻近触头的侧表面形成的间隔件。 间隔物可以抑制来自接触件的泄漏电流。

公开(公告)号：US07927723B1

公开(公告)日：2011-04-19

申请号：US11091524

申请日：2005-03-29

申请人： Angela T. Hui ,  Ning Cheng ,  Minh Van Ngo ,  Hirokazu Tokuno ,  Wenmei Li

发明人： Angela T. Hui ,  Ning Cheng ,  Minh Van Ngo ,  Hirokazu Tokuno ,  Wenmei Li

IPC分类号： G02B1/10 ,  G02B5/28 ,  B32B9/00 ,  B32B19/00

CPC分类号： G02B5/208

摘要： A film stack includes an interlayer dielectric formed over one or more devices. The film stack further includes a first layer having a high extinction coefficient formed on the interlayer dielectric and a second layer having a low extinction coefficient formed on the first layer. The first and second layers prevent ultraviolet induced damage to the one or more devices while minimizing reflectivity for lithographic processes.

摘要翻译： 膜堆叠包括在一个或多个器件上形成的层间电介质。 薄膜叠层还包括形成在层间电介质上的具有高消光系数的第一层和形成在第一层上的具有低消光系数的第二层。 第一层和第二层防止对一种或多种设备的紫外线诱发的损坏，同时最小化光刻工艺的反射率。