利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

136 条记录 (耗时 0.027 秒)

    Memory cell without halo implant
    71.
    发明申请
    Memory cell without halo implant 失效
    无光晕植入的记忆细胞

    公开(公告)号：US20050145935A1

    公开(公告)日：2005-07-07

    申请号：US10750566

    申请日：2003-12-31

    申请人： Ali Keshavarzi ,  Stephen Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek De

    发明人： Ali Keshavarzi ,  Stephen Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek De

    IPC分类号： G11C11/404 ,  H01L21/8239 ,  H01L27/02 ,  H01L27/105 ,  H01L27/108 ,  H01L29/76

    CPC分类号： G11C11/404 ,  G11C2211/4016 ,  H01L27/0207 ,  H01L27/0214 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108

    摘要： Some embodiments provide a memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with charge carriers of the second type. According to some embodiments, the body region, the source region, and the drain region are oriented in a first direction, the body region and the source region form a first junction, and the body region and the drain region form a second junction. Moreover, a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased. Some embodiments further include a transistor oriented in a second direction, wherein the second direction is not parallel to the first direction.

    摘要翻译： 一些实施例提供一种存储单元，其包括掺杂有第一类型的电荷载体的体区，设置在体区中的源极区，并掺杂有第二类型的电荷载流子，以及设置在体区中的掺杂电荷 第二种载体。 根据一些实施例，身体区域，源区域和漏极区域在第一方向上定向，身体区域和源区域形成第一结，并且体区域和漏区域形成第二结。 此外，在第一结无偏置的情况下，从体区到源极区的第一结的导电率基本上小于从体区到漏区的第二结的导电率，在第二结 是不偏不倚的 一些实施例还包括在第二方向上取向的晶体管，其中第二方向不平行于第一方向。

    Memory having bit line with resistor(s) between memory cells
    73.
    发明授权
    Memory having bit line with resistor(s) between memory cells 有权
    存储器与存储器单元之间的电阻器具有位线

    公开(公告)号：US07558097B2

    公开(公告)日：2009-07-07

    申请号：US11648399

    申请日：2006-12-28

    申请人： Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Nam Sung Kim ,  Vivek De

    发明人： Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Nam Sung Kim ,  Vivek De

    IPC分类号： G11C5/06

    CPC分类号： G11C5/063 ,  G11C11/413

    摘要： For one disclosed embodiment, an integrated circuit may comprise a memory array on the integrated circuit and access control circuitry on the integrated circuit. The memory array may have a bit line with one or more resistors along the bit line and may have a plurality of memory cells coupled to the bit line at a plurality of locations along the bit line. At least one resistor along the bit line may be between two locations at which memory cells are coupled to the bit line. The access control circuitry may be to select a memory cell coupled to the bit line and to sense a signal on the bit line from the selected memory cell. Other embodiments are also disclosed.

    摘要翻译： 对于一个公开的实施例，集成电路可以包括集成电路上的存储器阵列和集成电路上的访问控制电路。 存储器阵列可以具有沿着位线的一个或多个电阻器的位线，并且可以具有沿着位线的多个位置处耦合到位线的多个存储器单元。 沿着位线的至少一个电阻器可以在存储器单元耦合到位线的两个位置之间。 访问控制电路可以是选择耦合到位线的存储器单元并且感测来自所选存储单元的位线上的信号。 还公开了其他实施例。

    Memory having bit line with resistor(s) between memory cells
    74.
    发明申请
    Memory having bit line with resistor(s) between memory cells 有权
    存储器与存储器单元之间的电阻器具有位线

    公开(公告)号：US20080158932A1

    公开(公告)日：2008-07-03

    申请号：US11648399

    申请日：2006-12-28

    申请人： Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Nam Sung Kim ,  Vivek De

    发明人： Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Nam Sung Kim ,  Vivek De

    IPC分类号： G11C5/06

    CPC分类号： G11C5/063 ,  G11C11/413

    摘要： For one disclosed embodiment, an integrated circuit may comprise a memory array on the integrated circuit and access control circuitry on the integrated circuit. The memory array may have a bit line with one or more resistors along the bit line and may have a plurality of memory cells coupled to the bit line at a plurality of locations along the bit line. At least one resistor along the bit line may be between two locations at which memory cells are coupled to the bit line. The access control circuitry may be to select a memory cell coupled to the bit line and to sense a signal on the bit line from the selected memory cell. Other embodiments are also disclosed.

    摘要翻译： 对于一个公开的实施例，集成电路可以包括集成电路上的存储器阵列和集成电路上的访问控制电路。 存储器阵列可以具有沿着位线的一个或多个电阻器的位线，并且可以具有沿着位线的多个位置处耦合到位线的多个存储器单元。 沿着位线的至少一个电阻器可以在存储器单元耦合到位线的两个位置之间。 访问控制电路可以是选择耦合到位线的存储器单元并且感测来自所选存储单元的位线上的信号。 还公开了其他实施例。

    Method and apparatus for leakage compensation with full Vcc pre-charge
    75.
    发明授权
    Method and apparatus for leakage compensation with full Vcc pre-charge 有权
    具有全Vcc预充电的漏电补偿方法和装置

    公开(公告)号：US06801463B2

    公开(公告)日：2004-10-05

    申请号：US10273627

    申请日：2002-10-17

    申请人： Muhammad M. Khellah ,  Yibin Ye ,  Dinesh Somasekhar ,  Vivek De

    发明人： Muhammad M. Khellah ,  Yibin Ye ,  Dinesh Somasekhar ,  Vivek De

    IPC分类号： G11C700

    CPC分类号： G11C7/12

    摘要： A leakage compensation approach enabling full VCC precharge. An array of memory cells is coupled between a pair of bit lines. A precharge circuit precharges the pair of bit lines to substantially a supply voltage level and a leakage compensation circuit supplies a first compensation current to a first one of the bit lines to substantially compensate for leakage current supplied by the first bit line during a memory access operation directed to one of the plurality of memory cells.

    摘要翻译： 一种允许全VCC预充电的漏电补偿方式。 存储器单元阵列耦合在一对位线之间。 预充电电路将该对位线预充电到基本上的电源电压电平，并且泄漏补偿电路向位线中的第一位提供第一补偿电流，以在存储器访问操作期间基本上补偿由第一位线提供的泄漏电流 指向多个存储器单元中的一个。

    Method and apparatus for bus repeater tapering
    77.
    发明授权
    Method and apparatus for bus repeater tapering 有权
    总线中继器渐变的方法和装置

    公开(公告)号：US07684520B2

    公开(公告)日：2010-03-23

    申请号：US10334746

    申请日：2002-12-31

    申请人： James W. Tschanz ,  Muhammad M. Khellah ,  Yibin Ye ,  Vivek K. De

    发明人： James W. Tschanz ,  Muhammad M. Khellah ,  Yibin Ye ,  Vivek K. De

    IPC分类号： H04L27/00

    CPC分类号： H04L25/242

    摘要： A method and apparatus for bus repeater tapering. The sizing of repeaters on a portion of one transmission line is chosen to propagate a signal transition at a particular rate. The sizing of repeaters on a substantially parallel portion of another transmission line, is chosen to propagate a second signal transition at a different rate. Thus, the worst-case capacitance coupling factor between the two transmission lines may be reduced.

    摘要翻译： 一种用于总线中继器锥形化的方法和装置。 选择一个传输线路的一部分上的中继器的大小以传播特定速率的信号转换。 选择在另一传输线的基本平行部分上的中继器的尺寸以便以不同的速率传播第二信号转换。 因此，可以减小两条传输线之间的最坏情况电容耦合系数。

    Skewed repeater bus
    80.
    发明授权
    Skewed repeater bus 失效

    公开(公告)号：US06784688B2

    公开(公告)日：2004-08-31

    申请号：US10334410

    申请日：2002-12-30

    申请人： Muhammad M. Khellah ,  James W. Tschanz ,  Yibin Ye ,  Vivek K. De

    发明人： Muhammad M. Khellah ,  James W. Tschanz ,  Yibin Ye ,  Vivek K. De

    IPC分类号： H03K19003

    CPC分类号： H04L25/14

    摘要： According to some embodiments, provided are a first signal line, the first signal line coupled to a first repeater, the first repeater to convert a first signal from a received signal level to an output signal level, the first repeater to convert from a first signal level to a second signal level slower than from the second signal level to the first signal level, and a second signal line adjacent to the first signal line, the second signal line coupled to a second repeater adjacent to the first repeater, the second repeater to convert a second signal from a second received signal level to a second output signal level, the second repeater to convert from the first signal level to the second signal level slower than from the second signal level to the first signal level, wherein the received signal level is substantially equivalent to the second output signal level and wherein the second received signal level is substantially equivalent to the output signal level.