公开(公告)号：US5584038A

公开(公告)日：1996-12-10

申请号：US633905

申请日：1996-04-17

申请人： David B. Papworth ,  Andrew F. Glew ,  Michael A. Fetterman ,  Glenn J. Hinton ,  Robert P. Colwell ,  Steven J. Griffith ,  Shantanu R. Gupta ,  Narayan Hegde

发明人： David B. Papworth ,  Andrew F. Glew ,  Michael A. Fetterman ,  Glenn J. Hinton ,  Robert P. Colwell ,  Steven J. Griffith ,  Shantanu R. Gupta ,  Narayan Hegde

IPC分类号： G06F5/10 ,  G06F5/14 ,  G06F9/38 ,  G06F12/00

CPC分类号： G06F5/14 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3844 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863

摘要： An allocator assigns entries for a circular buffer. The allocator receives requests for storing data in entries of the circular buffer, and generates a head pointer to identify a starting entry in the circular buffer for which circular buffer entries are not allocated. In addition to pointing to an entry in the circular buffer, the head pointer includes a wrap bit. The allocator toggles the wrap bit each time the allocator traverses the linear queue of the circular buffer. A tail pointer is generated, including the wrap bit, to identify an ending entry in the circular buffer for which circular buffer entries are allocated. In response to the request for entries, the allocator sequentially assigns entries for the requests located between the head pointer and the tail pointer. The allocator has application for use in a microprocessor performing out-of-order dispatch anti speculative execution. The allocator is coupled to a reorder buffer, configured as a circular buffer, to permit allocation of entries. The allocator utilizes an all or nothing allocation policy, such that either all or no incoming instructions are allocated during an allocation period.

摘要翻译： 分配器为循环缓冲区分配条目。 分配器接收在循环缓冲器的条目中存储数据的请求，并且生成头指针以标识不分配循环缓冲器条目的循环缓冲器中的起始条目。 除了指向循环缓冲区中的条目之外，头指针还包括一个换行位。 每次分配器遍历循环缓冲区的线性队列时，分配器将切换换行。 生成尾指针，包括换行位，以标识分配循环缓冲区条目的循环缓冲区中的结尾条目。 响应于条目请求，分配器顺序分配位于头部指针和尾部指针之间的请求的条目。 分配器具有用于执行无序调度的推测执行的微处理器的应用程序。 分配器被耦合到配置为循环缓冲器的重排序缓冲器，以允许分配条目。 分配器利用全部或全部分配策略，使得在分配周期期间分配全部或者没有传入指令。

公开(公告)号：US5561814A

公开(公告)日：1996-10-01

申请号：US171528

申请日：1993-12-22

申请人： Andrew F. Glew ,  Glenn J. Hinton ,  David B. Papworth ,  Michael A. Fetterman ,  Robert P. Colwell ,  Frederick J. Pollack

发明人： Andrew F. Glew ,  Glenn J. Hinton ,  David B. Papworth ,  Michael A. Fetterman ,  Robert P. Colwell ,  Frederick J. Pollack

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F13/10

CPC分类号： G06F12/0888 ,  G06F12/1027 ,  G06F2212/206

摘要： A circuit comprising a number of address range registers and complimentary decoding/matching circuits is provided to a processor for determining the memory type of a physical address, thereby allowing memory type to be determined as soon as the physical address is available in an execution stage preceding cache access. Additionally, a memory type field is provided to each address translation lookaside buffer entry of the data and instruction memory subsystem for storing the determined memory type. The memory type determination circuit is disposed in the page miss handler, thereby allowing memory type to be determined at the same time when the physical address is determined.

摘要翻译： 包括多个地址范围寄存器和互补解码/匹配电路的电路被提供给处理器，用于确定物理地址的存储器类型，由此一旦物理地址在执行阶段中可用，就允许确定存储器类型 缓存访问。 此外，存储器类型字段被提供给用于存储确定的存储器类型的数据和指令存储器子系统的每个地址转换后备缓冲器入口。 存储器类型确定电路设置在页面未命中处理器中，从而允许在确定物理地址的同时确定存储器类型。

公开(公告)号：US5519864A

公开(公告)日：1996-05-21

申请号：US172737

申请日：1993-12-27

申请人： Robert W. Martell ,  Glenn J. Hinton

发明人： Robert W. Martell ,  Glenn J. Hinton

IPC分类号： G06F9/38 ,  G06F9/06

CPC分类号： G06F9/3855 ,  G06F9/3836 ,  G06F9/3857

摘要： Entries in a reservation station are efficiently scanned to find data-ready instructions for dispatch. A pseudo-FIFO scheduling approach is implemented wherein, rather than scanning every entry in the reservation station, the reservation station is segmented into groups of entries with each entry being scanned to determine which has the oldest entry in it. It is from the group of entries having the oldest entry that a ready pointer is cycled to search for data-ready instructions for dispatch to waiting execution units.

摘要翻译： 有效地扫描保留站中的条目以查找数据就绪指令进行发送。 实现伪FIFO调度方法，其中，不是扫描保留站中的每个条目，保留站被分段成条目组，其中每个条目被扫描以确定哪个条目具有其中最早的条目。 来自具有最早条目的条目组可以循环准备好的指针以搜索用于发送到等待执行单元的数据就绪指令。

公开(公告)号：US09378142B2

公开(公告)日：2016-06-28

申请号：US13994731

申请日：2011-09-30

申请人： Raj K. Ramanujan ,  Rajat Agarwal ,  Glenn J. Hinton

发明人： Raj K. Ramanujan ,  Rajat Agarwal ,  Glenn J. Hinton

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F12/02 ,  G11C7/10 ,  G11C13/00

CPC分类号： G06F12/0811 ,  G06F12/0246 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0888 ,  G06F12/0893 ,  G06F2212/205 ,  G06F2212/283 ,  G06F2212/6046 ,  G06F2212/621 ,  G06F2212/7201 ,  G11C7/1045 ,  G11C7/1072 ,  G11C13/0004 ,  G11C14/0045

摘要： A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” In one embodiment, the “near memory” is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.

摘要翻译： 描述了用于集成包括计算机系统内的非易失性存储器层的存储器和存储层级的系统和方法。 在一个实施例中，PCMS存储器件被用作层次结构中的一层，有时被称为“远存储器”。更高性能的存储器件例如放置在远存储器之前的DRAM，并用于掩盖某些性能限制 远记忆 这些更高性能的存储器件被称为“近存储器”。在一个实施例中，“近端存储器”被配置为以多种不同的操作模式操作，包括（但不限于）第一模式，其中近端存储器 作为远存储器的存储器高速缓冲存储器和第二模式，其中近距离存储器被分配有系统地址空间的第一地址范围，远处存储器被分配系统地址空间的第二地址范围，其中第一范围和 第二个范围代表整个系统地址空间。

公开(公告)号：US09146873B2

公开(公告)日：2015-09-29

申请号：US13436337

申请日：2012-03-30

申请人： Anil Vasudevan ,  Glenn J. Hinton ,  Yadong Li

发明人： Anil Vasudevan ,  Glenn J. Hinton ,  Yadong Li

IPC分类号： G06F3/00 ,  G06F12/08 ,  H04L12/861 ,  G06F5/10

CPC分类号： G06F12/084 ,  G06F5/10 ,  H04L49/90

摘要： Examples are disclosed for establishing a window for a queue structure maintained in a cache for a processing element for a network device. The processing element may be configured to operate in cooperation with an input/output device such as a network interface card. In some of these examples, the window may include portions of the queue structure having identifiers to active allocated buffers maintained in memory for the network device. The active allocated buffers may be configured to maintain or store data received or to be forwarded by the input/output device. For these examples, the window may be adjusted based on information gathered while the identifiers are read from or written to the portions of the queue structure.

摘要翻译： 公开了用于建立用于网络设备的处理元件的高速缓存中维护的队列结构的窗口的示例。 处理元件可以被配置为与诸如网络接口卡的输入/输出设备协作操作。 在这些示例中的一些示例中，窗口可以包括具有对于网络设备的存储器中维护的主动分配缓冲区的标识符的队列结构的部分。 活动分配的缓冲器可以被配置为维护或存储由输入/输出设备接收或要转发的数据。 对于这些示例，可以基于从标识符从队列结构的部分读取或写入标识符时收集的信息来调整窗口。

公开(公告)号：US20140380085A1

公开(公告)日：2014-12-25

申请号：US13924585

申请日：2013-06-23

申请人： Willam C. Rash ,  Scott D. Hanh ,  Glenn J. Hinton

发明人： Willam C. Rash ,  Scott D. Hanh ,  Glenn J. Hinton

IPC分类号： G06F11/14 ,  G06F11/07

CPC分类号： G06F11/0772 ,  G06F11/0724 ,  G06F11/1415 ,  G06F11/142 ,  G06F11/1443 ,  G06F2201/815

摘要： A technology for implementing a method for a machine check architecture environment. A method of the disclosure includes obtaining an occurrence of an error. The occurrence of the error causes a non-microcoded processing device to enter an error monitoring state. The method further processes the error using a dedicated memory portion for the error monitoring state while the non-microcoded processing device is in the error monitoring state. The error monitoring state is dedicated to error processing. The method further determines information associated with the error. The information associated with the error is in a predefined format.

摘要翻译： 一种用于实现机器检查架构环境的方法的技术。 本公开的方法包括获得错误的发生。 错误的发生导致非微编码处理设备进入错误监视状态。 该方法使用专用存储器部分处理错误，用于错误监视状态，而非微编码处理设备处于错误监视状态。 错误监控状态专用于错误处理。 该方法进一步确定与错误相关联的信息。 与错误相关联的信息是预定义的格式。

公开(公告)号：US06694426B2

公开(公告)日：2004-02-17

申请号：US10164774

申请日：2002-06-06

申请人： Patrice Roussel ,  Glenn J. Hinton ,  Shreekant S. Thakkar ,  Brent R. Boswell ,  Karol F. Menezes

发明人： Patrice Roussel ,  Glenn J. Hinton ,  Shreekant S. Thakkar ,  Brent R. Boswell ,  Karol F. Menezes

IPC分类号： G06F1500

CPC分类号： G06F9/30014 ,  G06F9/30036 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3875 ,  G06F9/3885

摘要： A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.

公开(公告)号：US06425073B1

公开(公告)日：2002-07-23

申请号：US09805280

申请日：2001-03-13

申请人： Patrice Roussel ,  Glenn J. Hinton ,  Shreekant S. Thakkar ,  Brent R. Boswell ,  Karol F. Menezes

发明人： Patrice Roussel ,  Glenn J. Hinton ,  Shreekant S. Thakkar ,  Brent R. Boswell ,  Karol F. Menezes

IPC分类号： G06F900

摘要： A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.

公开(公告)号：US06393550B1

公开(公告)日：2002-05-21

申请号：US08532225

申请日：1995-09-19

申请人： Michael A. Fetterman ,  Glenn J. Hinton ,  Robert W. Martell ,  David B. Papworth

发明人： Michael A. Fetterman ,  Glenn J. Hinton ,  Robert W. Martell ,  David B. Papworth

IPC分类号： G06F930

CPC分类号： G06F9/30167 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： Maximum throughput or “back-to-back” scheduling of dependent instructions in a pipelined processor is achieved by maximizing the efficiency in which the processor determines the availability of the source operands of a dependent instruction and provides those operands to an execution unit executing the dependent instruction. These two operations are implemented through a number of mechanisms. One mechanism for determining the availability of source operands, and hence the readiness of a dependent instruction for dispatch to an available execution unit, relies on the early setting of a source valid bit during allocation when a source operand is a retired or immediate value. This allows the ready logic of a reservation station to begin scheduling the instruction for dispatch.

摘要翻译： 通过最大化处理器确定依赖指令的源操作数的可用性的效率，并将这些操作数提供给执行依赖的执行单元，从而实现流水线处理器中相关指令的最大吞吐量或“背对背” 指令。 这两个操作通过多种机制来实现。 用于确定源操作数的可用性以及因此用于调度到可用执行单元的依赖指令的准备状态的一种机制依赖于在源操作数为退休或即时值时在分配期间早期设置源有效位。 这允许保留站的就绪逻辑开始调度发送指令。

公开(公告)号：US06170038A

公开(公告)日：2001-01-02

申请号：US09447078

申请日：1999-11-22

申请人： Robert F. Krick ,  Glenn J. Hinton ,  Michael D. Upton ,  David J. Sager ,  Chan W. Lee

发明人： Robert F. Krick ,  Glenn J. Hinton ,  Michael D. Upton ,  David J. Sager ,  Chan W. Lee

IPC分类号： G06F926

CPC分类号： G06F12/0875

摘要： A cache memory is constituted with a data array and control logic. The data array includes a number of data lines, and the control logic operates to store a number of trace segments of instructions in the data lines, including trace segments that span multiple data lines. In one embodiment, each trace segment includes one or more trace segment members having one or more instructions, with each trace segment member occupying one data line, and the data lines of a multi-line trace segment being sequentially associated (logically). Retrieval of the trace segment members of a multi-line trace segment is accomplished by first locating the data line storing the first trace segment member of the trace segment, and then successively locating the remaining data lines storing the remaining trace segment members based on the data lines' logical sequential associations.

摘要翻译： 高速缓冲存储器由数据阵列和控制逻辑构成。 数据阵列包括许多数据线，并且控制逻辑操作以在数据线中存储多条迹线段，包括跨越多个数据线的迹线段。 在一个实施例中，每个跟踪段包括具有一个或多个指令的一个或多个跟踪段成员，每个跟踪段成员占据一个数据线，并且多行跟踪段的数据线被顺序地相关联（逻辑地）。 通过首先定位存储跟踪段的第一跟踪段成员的数据线，然后基于数据连续定位存储剩余跟踪段成员的剩余数据线，来检索多行跟踪段的跟踪段成员 行的逻辑顺序关联。