公开(公告)号：US20070085210A1

公开(公告)日：2007-04-19

申请号：US11307161

申请日：2006-01-26

申请人： Feng-Yu Hsu ,  Chih-Chien Liu ,  Chun-Chieh Huang ,  Jei-Ming Chen ,  Shu-Jen Sung

发明人： Feng-Yu Hsu ,  Chih-Chien Liu ,  Chun-Chieh Huang ,  Jei-Ming Chen ,  Shu-Jen Sung

IPC分类号： H01L23/52

CPC分类号： H01L21/7682 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure is described, disposed on a substrate with a conductive part thereon and including a first porous low-k layer on the substrate, a damascene structure in the first porous low-k layer electrically connecting with the conductive part, a second porous low-k layer over the first porous low-k layer and the damascene structure, and a UV cutting layer at least between the first and the second porous low-k layers, wherein the UV cutting layer is a UV reflection layer or a UV reflection-absorption layer.

摘要翻译： 描述了布置在其上具有导电部分的基板上并且在基板上包括第一多孔低k层的基板上的互连结构，与导电部分电连接的第一多孔低k层中的镶嵌结构，第二多孔低 -k层，以及至少在第一和第二多孔低k层之间的UV切割层，其中UV切割层是UV反射层或UV反射层， 吸收层。

公开(公告)号：US20060286794A1

公开(公告)日：2006-12-21

申请号：US11322140

申请日：2005-12-28

申请人： Chin-Hsiang Lin ,  Chih-Chien Liu

发明人： Chin-Hsiang Lin ,  Chih-Chien Liu

IPC分类号： H01L21/4763 ,  H01L23/48

CPC分类号： H01L21/76826 ,  H01L21/76811 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11556

摘要： A method of fabricating a stacked structure for forming a damascene process is described. A doped dielectric layer is formed on a substrate. A surface treatment is performed to the dielectric layer to make the dopant concentration in an upper surface layer of the dielectric layer lower than that in the other portions of the dielectric layer. A metal hard mask is then formed on the dielectric layer. Since the dopant conc. in the upper surface layer of the dielectric layer is lowered, the reaction between the metal hard mask and the dopant in the dielectric layer can be inhibited.

摘要翻译： 描述了一种制造用于形成镶嵌工艺的层叠结构的方法。 在衬底上形成掺杂介电层。 对电介质层进行表面处理，使得电介质层的上表面层中的掺杂剂浓度低于电介质层的其它部分中的掺杂剂浓度。 然后在电介质层上形成金属硬掩模。 由于掺杂剂浓度 在电介质层的上表层降低时，可以抑制金属硬掩模与电介质层中的掺杂剂之间的反应。

公开(公告)号：US20060165913A1

公开(公告)日：2006-07-27

申请号：US11046049

申请日：2005-01-27

申请人： Bella Chen ,  Chin-Hsiang Lin ,  Chih-Chien Liu ,  Jerander Lai

发明人： Bella Chen ,  Chin-Hsiang Lin ,  Chih-Chien Liu ,  Jerander Lai

IPC分类号： H05H1/24

CPC分类号： C23C16/4405 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02334 ,  H01L21/02337 ,  H01L21/31633 ,  H01L21/76826

摘要： A method of reducing the number of particles on a low-k material layer is described. The low-k material layer is formed by a plasma enhanced chemical vapor deposition process, wherein a reaction gas, a cleaning gas, a high-frequency power and a low-frequency power are used. The method comprises turning off the reaction gas and the low-frequency power after the low-k material layer is formed, and continuing to provide the cleaning gas during a delay time.

摘要翻译： 描述了一种减少低k材料层上的颗粒数量的方法。 低k材料层通过等离子体增强化学气相沉积法形成，其中使用反应气体，清洁气体，高频功率和低频功率。 该方法包括在形成低k材料层之​​后关闭反应气体和低频功率，并且在延迟时间内继续提供清洁气体。

公开(公告)号：US06905938B2

公开(公告)日：2005-06-14

申请号：US10315128

申请日：2002-12-10

申请人： Ming-Sheng Yang ,  Chih-Chien Liu

发明人： Ming-Sheng Yang ,  Chih-Chien Liu

IPC分类号： H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/76

CPC分类号： H01L21/76801 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/31629 ,  H01L21/318 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a method for forming low dielectric constant inter-metal dielectric layer. The method includes providing a semiconductor substrate and forming a first dielectric layer on the semiconductor substrate. Conductor structures are formed in the first dielectric layer. The partial first dielectric layer is removed by using the conductor structures as etching mask. A second dielectric layer is formed between the conductor structures, which has a dielectric constant smaller than the first dielectric layer. The second dielectric layer also alternatively has air voids contained therein to reduce dielectric constant.

摘要翻译： 本发明提供一种形成低介电常数金属间介电层的方法。 该方法包括提供半导体衬底并在半导体衬底上形成第一电介质层。 在第一电介质层中形成导体结构。 通过使用导体结构作为蚀刻掩模来去除部分第一介电层。 在导体结构之间形成第二电介质层，导体结构的介电常数小于第一介电层。 第二电介质层也可选择地含有空气，以减少介电常数。

公开(公告)号：US06410106B1

公开(公告)日：2002-06-25

申请号：US09759570

申请日：2001-01-11

申请人： Cheng-Yuan Tsai ,  Chih-Chien Liu ,  Ming-Sheng Yang

发明人： Cheng-Yuan Tsai ,  Chih-Chien Liu ,  Ming-Sheng Yang

IPC分类号： H05H124

摘要： A method is used to form an intermetal dielectric layer. According to the invention, an unbiased-unclamped fluorinated silicate glass layer used as a protection layer is formed by high density plasma chemical vapor deposition on a biased-clamped fluorinated silicate glass layer formed by high density plasma chemical vapor deposition to prevent the biased-clamped fluorinated silicate glass layer from being exposed in a planarization process.

公开(公告)号：US06319814B1

公开(公告)日：2001-11-20

申请号：US09417830

申请日：1999-10-12

申请人： Cheng-Yuan Tsai ,  Chih-Chien Liu ,  Juan-Yuan Wu

发明人： Cheng-Yuan Tsai ,  Chih-Chien Liu ,  Juan-Yuan Wu

IPC分类号： H01L214763

CPC分类号： H01L21/76834 ,  H01L21/02131 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31629 ,  H01L21/7681 ,  H01L21/76832

摘要： A method for fabricating dual damascene is to form an undoped silicate glass (USG) liner before forming a fluorinated silicate glass (FSG) layer which serves as an inter-metal dielectric (IMD) layer on a semiconductor substrate. As a result, the surface sensitivity is eliminated, while a FSG layer with a more uniform thickness and a higher reliability is obtained. In addition, the USG liner increases the adhesion between the FSG layer and other material layers, while no particles are easily formed thereon.

摘要翻译： 制造双镶嵌的方法是在形成在半导体衬底上作为金属间电介质（IMD）层的氟化硅酸盐玻璃（FSG）层之前形成未掺杂的硅酸盐玻璃（USG）衬垫。 结果，消除了表面灵敏度，而获得了具有更均匀厚度和更高可靠性的FSG层。 此外，USG衬垫增加了FSG层和其它材料层之间的粘附性，而在其上不容易形成颗粒。

公开(公告)号：US06261977B1

公开(公告)日：2001-07-17

申请号：US09391357

申请日：1999-09-08

申请人： Cheng-Yuan Tsai ,  Chih-Chien Liu ,  Juan-Yuan Wu

发明人： Cheng-Yuan Tsai ,  Chih-Chien Liu ,  Juan-Yuan Wu

IPC分类号： H01L21324

CPC分类号： H01L21/67069 ,  H01L21/6831 ,  H01L21/6833 ,  Y10S438/905 ,  Y10S438/906 ,  Y10S438/907

摘要： The present invention relates to a method for preventing an electrostatic chuck positioned at the bottom of a plasma vacuum chamber from being corroded during a cleaning process. The electrostatic chuck comprises a conductive substrate functioned as a lower electrode in a plasma process, and an insulating layer on the conductive substrate to electrically isolate the semiconductor wafer and the conductive substrate. The cleaning process involves a plasma process in which a fluorine-contained gas is injected into the plasma vacuum chamber to remove the chemical layer on the inner wall of the plasma vacuum chamber. A ceramic shutter made of SiC material is reposed on the electrostatic chuck and a high DC voltage is applied to the conductive substrate and the ceramic shutter which causes the ceramic shutter and the electrostatic chuck tightly stick together due to an electrostatic reaction. By doing so, the fluorine-contained gas cannot corrode the insulating layer under the ceramic shutter through the gap between the ceramic shutter and the electrostatic chuck.

摘要翻译： 本发明涉及一种防止位于等离子体真空室底部的静电卡盘在清洗过程中被腐蚀的方法。 静电卡盘包括在等离子体工艺中用作下电极的导电基板和导电基板上的绝缘层，以电绝缘半导体晶片和导电基板。 清洗过程涉及等离子体处理，其中将含氟气体注入到等离子体真空室中以除去等离子体真空室的内壁上的化学层。 由SiC材料制成的陶瓷快门被放置在静电卡盘上，并且高导电性基板和陶瓷快门上施加高的直流电压，导致陶瓷快门和静电卡盘由于静电反应紧紧地粘在一起。 通过这样做，含氟气体不能通过陶瓷快门和静电卡盘之间的间隙腐蚀陶瓷快门下面的绝缘层。

公开(公告)号：US06174793B1

公开(公告)日：2001-01-16

申请号：US09415798

申请日：1999-10-11

申请人： Cheng-Yuan-Chen Tsai ,  Chih-Chien Liu ,  Juan-Yuan Wu

发明人： Cheng-Yuan-Chen Tsai ,  Chih-Chien Liu ,  Juan-Yuan Wu

IPC分类号： H01L213205

CPC分类号： H01L21/76867 ,  H01L21/76838 ,  H01L21/7685 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for enhancing adhesion ability between copper and silicon nitride is disclosed. The present method comprises following steps: first, provide a substrate and then form a copper layer on the substrate; second, form a copper phosphide layer on the copper layer; and finally, form a silicon nitride layer on the copper phosphide layer. Herein, the copper phosphide layer is formed by a plasma enhanced chemical vapor deposition process. Therefore, any copper oxide layer that covers copper layer is replaced by the silicon phosphide layer and then adhesion between copper and silicon nitride is improved. Moreover, the silicon phosphide comprises two advantages: low resistance than copper oxide and efficiently prevent copper diffuses into surrounding dielectric layer.

摘要翻译： 公开了一种提高铜和氮化硅之间粘附能力的方法。 本发明方法包括以下步骤：首先提供衬底，然后在衬底上形成铜层; 第二，在铜层上形成磷化铜层; 最后在磷化铜层上形成氮化硅层。 这里，通过等离子体增强化学气相沉积工艺形成磷化铜层。 因此，覆盖铜层的任何铜氧化物层被磷化硅层代替，然后提高铜和氮化硅之间的粘附。 此外，磷化硅具有两个优点：电阻低于铜氧化物，并有效地防止铜扩散到周围的电介质层。

公开(公告)号：US20160026270A1

公开(公告)日：2016-01-28

申请号：US14503425

申请日：2014-10-01

申请人： Chih-Chien Liu ,  Chun-Sheng Chen

发明人： Chih-Chien Liu ,  Chun-Sheng Chen

IPC分类号： G06F3/0354 ,  G06F3/041

CPC分类号： G06F3/03543 ,  G06F3/03547 ,  G06F3/038 ,  G06F3/0416 ,  G06F3/04883

摘要： An operating method of an electronic apparatus and a touch apparatus are provided. In the method, a touch action by a user on a touch panel is detected through a controller of the touch apparatus, so as to obtain a contact region touched by the touch action on the touch panel. Subsequently, whether the touch action includes a palm touch is determined based on a size of the contact region. Under the situation that the touch action includes the palm touch, palm touching information corresponding to the palm touch is transformed into mouse controlling information through a mouse simulating device of the touch apparatus. Further, the mouse controlling information is sent to a mouse driver through the mouse simulating device, such that the mouse driver executes mouse operation based on the mouse controlling information.

摘要翻译： 提供了电子设备和触摸设备的操作方法。 在该方法中，通过触摸装置的控制器检测用户对触摸面板的触摸动作，以便获得触摸面板上的触摸动作所触摸的接触区域。 随后，基于接触区域的大小确定触摸动作是否包括手掌触摸。 在触摸动作包括手掌触摸的情况下，通过触摸装置的鼠标模拟装置将与手掌触摸对应的手掌触摸信息转换成鼠标控制信息。 此外，通过鼠标模拟装置将鼠标控制信息发送给鼠标驱动器，使得鼠标驱动器基于鼠标控制信息执行鼠标操作。

公开(公告)号：US09184100B2

公开(公告)日：2015-11-10

申请号：US13206533

申请日：2011-08-10

申请人： Teng-Chun Tsai ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Cheng Chien ,  Chin-Fu Lin

发明人： Teng-Chun Tsai ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Cheng Chien ,  Chin-Fu Lin

IPC分类号： H01L27/092 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/10

CPC分类号： H01L21/845 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/165

摘要： A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.

摘要翻译： 半导体器件包括半导体衬底，至少第一鳍结构，至少第二鳍结构，第一栅极，第二栅极，第一源极/漏极区域和第二源极/漏极区域。 半导体衬底至少具有第一有源区以配置第一鳍结构和至少第二有源区以配置第二鳍结构。 与第一/第二栅极部分重叠的第一/第二鳍结构具有第一/第二应力，第一应力和第二应力彼此不同。 第一/第二源极/漏极区域设置在第一/第二栅极的两侧的第一/第二鳍结构中。