公开(公告)号：US20180253643A1

公开(公告)日：2018-09-06

申请号：US15449071

申请日：2017-03-03

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Brent Buchanan ,  Miao Hu ,  John Paul Strachan

IPC: G06N3/063 ,  G11C13/00 ,  H03M1/12

CPC classification number: G06N3/0635 ,  G06F7/5443 ,  G06F2207/4802 ,  G06F2207/4824 ,  G11C13/0069 ,  H03M1/1245

Abstract: An example electronic device includes a crossbar array, row driver circuitry, and column output circuits for each of the column lines of the crossbar array. The crossbar array may include row lines, column lines, and memristors that each are connected between one of the row lines and one of the column lines. The row driver circuitry may be to apply a plurality of analog voltages to a first node during a plurality of time periods, respectively, and, for each of the row lines, selectively connect the row line to the first node during one of the plurality of time periods based on a digital input vector. The column output circuits may each include: an integration capacitor, a switch that is controlled by an integration control signal, and current mirroring circuitry. The current mirroring circuitry may be to, when the switch is closed, flow an integration current to or from an electrode of the integration capacitor whose magnitude mirrors a current flowing on the corresponding column line. The integration control signal may be to close the switch for a specified amount of time during each of the plurality of time periods.

公开(公告)号：US10056141B2

公开(公告)日：2018-08-21

申请号：US15318000

申请日：2014-07-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Brent Buchanan

IPC: G11C16/10 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0002 ,  G11C13/0061 ,  G11C16/10 ,  G11C29/026 ,  G11C29/028 ,  G11C2013/0052 ,  G11C2213/15

Abstract: An example device in accordance with an aspect of the present disclosure includes a first module, a second module, and a third module. The first module is coupled to an element whose status is to be determined, and the first module is to receive an input current that increases over time. The second module is to perform a temporal derivative of a voltage across the element. The third module is to provide an output signal based on a current behavior of the element, according to a change in voltage as a function of a change in current.

公开(公告)号：US20180218771A1

公开(公告)日：2018-08-02

申请号：US15418040

申请日：2017-01-27

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Brent Buchanan ,  Le Zheng ,  John Paul Strachan

IPC: G11C13/00 ,  G06F17/16

CPC classification number: G11C13/0069 ,  G06F17/16

Abstract: Examples disclosed herein relate to programming a first conductance of a first resistive memory device based on a first target value. The first conductance of the first resistive memory device is measured to determine a deviation of the first resistive memory device from the first target value. A second target value of a second resistive memory device is adjusted based on the deviation, and a second conductance of the second resistive memory device is programmed based on the adjusted second target value.

公开(公告)号：US20180121416A1

公开(公告)日：2018-05-03

申请号：US15336907

申请日：2016-10-28

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Brent Buchanan ,  Le Zheng ,  John Paul Strachan

IPC: G06F17/27

CPC classification number: G06F17/2735

Abstract: Comparators may be associated with dictionary entries. In one aspect, a dictionary entry may store a dictionary word. A register may store an input word. A comparator associated with the dictionary entry may compare the dictionary word and the input word. The comparison may be a bit by bit comparison. The comparator may output a signal indicating if the dictionary word is less than the input word, equal to the input word, or greater than the input word. The output may indicate indeterminate when the comparison is not yet complete.

公开(公告)号：US09934857B2

公开(公告)日：2018-04-03

申请号：US15228559

申请日：2016-08-04

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Le Zheng ,  Brent Buchanan ,  John Paul Strachan

IPC: G11C15/00 ,  G11C15/04

CPC classification number: G11C15/046

Abstract: An example ternary content addressable memory. A bit cell of the memory may include a first memristor that has a first terminal that is connected to a first data line and a second terminal that is selectively connected to a second data line via a first switching transistor. The bit cell may also include a second memristor that has a first terminal that is connected to a third data line and a second terminal that is selectively connected to a fourth data line via a second switching transistor. The bit cell may also include a first match-line transistor and a second match-line transistor that are connected in series between a first rail and a match line, with a gate of the first match-line transistor being connected to the second terminal of the first memristor, and a gate of the second match-line transistor being connected to the second terminal of the second memristor.

公开(公告)号：US09928904B2

公开(公告)日：2018-03-27

申请号：US15500046

申请日：2014-09-26

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Brent Buchanan ,  Le Zheng

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/003 ,  G11C11/1659 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0069 ,  G11C2213/74 ,  G11C2213/79

Abstract: An example device in accordance with an aspect of the present disclosure includes a plurality of bit-cells coupled as an array. A bit-cell includes a first switch element, a second switch element, and a memory element coupled at a node. The plurality of bit-cells are coupled as the array based on a first bit-cell's memory element being coupled to a second bit-cell's node.

公开(公告)号：US09847128B2

公开(公告)日：2017-12-19

申请号：US15311594

申请日：2014-06-20

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Brent Buchanan ,  Richard James Auletta

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0059 ,  G11C13/0002 ,  G11C13/0064 ,  G11C13/0069

Abstract: In the examples provided herein, a voltage driver module applies an increasing voltage to a memristive memory cell until a resistance of the cell switches to a target resistance. A monitoring module monitors a switching voltage at which the resistance of the cell switches to the target resistance, or an application duration of the increasing voltage to the cell. Additionally, a controller performs an action to protect data stored by the cell upon determining that the switching voltage exceeds a target voltage.

公开(公告)号：US09847126B2

公开(公告)日：2017-12-19

申请号：US15325358

申请日：2014-10-24

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Brent Buchanan ,  R. Stanley Williams

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/16

CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C13/0002 ,  G11C13/0007 ,  G11C2013/0045 ,  G11C2013/0054

Abstract: A method of increasing a read margin in a memory cell may include sensing an input current created from the application of a read voltage across a memristive device, squaring the input current, and comparing the squared input current to a reference current. A memristive device may include a memristor and a sense amplifier communicatively coupled to the memristor wherein a sensed input current created from the application of a reference voltage across a memristor is squared and wherein the sense amplifier compares the squared input current to a reference current.

公开(公告)号：US09842647B1

公开(公告)日：2017-12-12

申请号：US15267124

申请日：2016-09-15

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： John Paul Strachan ,  Brent Buchanan ,  Emmanuelle Merced Grafals

IPC: G11C11/00 ,  G11C13/00 ,  G11C29/52

CPC classification number: G11C13/0069 ,  G11C13/0033 ,  G11C27/00 ,  G11C29/52

Abstract: Examples include a method of programming resistive random access memory (RRAM) array for analog computations. In some examples, a selected RRAM cell of the RRAM array may be programmed with a selected target conductance and a programmed conductance error of the selected RRAM cell may be determined. A neighboring RRAM cell may be programmed with an error corrected target conductance that is a function of a neighboring target conductance and the programmed conductance error of the selected RRAM cell. The neighboring RRAM cell may be in a same row or a same column as the selected RRAM cell. The selected RRAM cell and neighboring RRAM cell are programmed such that the RRAM array is programmed for an analog computation.

公开(公告)号：US09837154B2

公开(公告)日：2017-12-05

申请号：US15500472

申请日：2015-04-15

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Brent Buchanan

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0064 ,  G11C13/0097 ,  G11C2013/0066 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2213/77

Abstract: One example includes a resistive random access memory (RRAM) system. The system includes a resistive memory element to store a binary state based on a resistance of the resistive memory element. The system also includes an RRAM write circuit to generate a current through the resistive memory element to provide a write voltage across the resistive memory element to set the resistance of the resistive memory element. The system further includes a write shutoff circuit to monitor a change in the write voltage as a function of time to deactivate the RRAM write circuit in response to a change in the binary state of the resistive memory element.