公开(公告)号：US08077506B2

公开(公告)日：2011-12-13

申请号：US12969526

申请日：2010-12-15

申请人： Ming-Hsiu Lee ,  Yi-Chou Chen

发明人： Ming-Hsiu Lee ,  Yi-Chou Chen

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/0092

摘要： A method of programming a phase change device includes selecting a desired threshold voltage (Vth) and applying a programming pulse to a phase change material in the phase change device. The applying of the programming pulse includes applying a quantity of energy to the phase change material to drive at least a portion of this material above a melting energy level. A portion of the energy applied to the phase change material is allowed to dissipate below the melting energy level. The shape of the energy dissipation from the phase change material is controlled until the energy applied to the phase change material is less than a quenched energy level, to cause the phase change device to have the desired Vth. A remaining portion of the energy applied to the phase change material is allowed to dissipate to an environmental level.

公开(公告)号：US08064247B2

公开(公告)日：2011-11-22

申请号：US12488795

申请日：2009-06-22

申请人： Ming-Hsiu Lee ,  Chieh-Fang Chen ,  Yen-Hao Shih ,  Yu Zhu

发明人： Ming-Hsiu Lee ,  Chieh-Fang Chen ,  Yen-Hao Shih ,  Yu Zhu

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0071 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/33 ,  G11C2213/79 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625

摘要： Memory devices described herein are programmed and erased by physical segregation of an electrically insulating layer out of a memory material to establish a high resistance state, and by re-absorption of at least a portion of the electrically insulating layer into the memory material to establish a low resistance state. The physical mechanism of programming and erasing includes movement of structure vacancies to form voids, and/or segregation of doping material and bulk material, to create the electrically insulating layer consisting of voids and/or dielectric doping material along an inter-electrode current path between electrodes.

摘要翻译： 通过将电绝缘层从存储材料中物理分离出来以建立高电阻状态，并且通过将电绝缘层的至少一部分再吸收到存储材料中以建立 低电阻状态。 编程和擦除的物理机制包括结构空位的移动以形成空隙，和/或掺杂材料和体材料的偏析，以产生由空隙和/或介电掺杂材料构成的电绝缘层，沿着电极间电流通路 电极。

公开(公告)号：US07944740B2

公开(公告)日：2011-05-17

申请号：US12564904

申请日：2009-09-22

申请人： Chung H. Lam ,  Ming-Hsiu Lee ,  Thomas Nirschi ,  Bipin Rajendran

发明人： Chung H. Lam ,  Ming-Hsiu Lee ,  Thomas Nirschi ,  Bipin Rajendran

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2013/0092

摘要： A phase change memory device and a method for programming the same. The method includes determining a characterized lowest SET current and corresponding SET resistance for the phase change memory device. The method includes determining a characterized RESET current slope for the phase change memory device. The method also includes calculating a first current amplitude for a RESET pulse based on the characterized lowest SET current and the characterized RESET current slope. The method includes applying the RESET pulse to a target memory cell in the phase change memory device and measuring the resistance of the target memory cell. If the measured resistance is substantially less than a target resistance, the method further includes applying one or more additional RESET pulses. In one embodiment of the invention, the one or more additional RESET pulses have current amplitudes greater than a previously applied RESET pulse.

摘要翻译： 相变存储器件及其编程方法。 该方法包括确定用于相变存储器件的特征最低的SET电流和相应的SET电阻。 该方法包括确定用于相变存储器件的特征化的RESET电流斜率。 该方法还包括基于所表征的最低SET电流和表征的RESET电流斜率来计算RESET脉冲的第一电流幅度。 该方法包括将RESET脉冲施加到相变存储器件中的目标存储单元并测量目标存储单元的电阻。 如果所测量的电阻远小于目标电阻，该方法还包括应用一个或多个附加的RESET脉冲。 在本发明的一个实施例中，一个或多个附加的RESET脉冲的电流幅度大于先前施加的RESET脉冲。

公开(公告)号：US07869270B2

公开(公告)日：2011-01-11

申请号：US12345384

申请日：2008-12-29

申请人： Ming-Hsiu Lee

发明人： Ming-Hsiu Lee

IPC分类号： G11C11/00

CPC分类号： G11C13/0038 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/79

摘要： Memory devices and methods for operating such devices are described herein. A method is described herein for operating a memory cell comprising phase change material and programmable to a plurality of resistance states including a high resistance state and a lower resistance state. The method comprises applying a first bias arrangement to the memory cell to establish the lower resistance state, the first bias arrangement comprising a first voltage pulse. The method further comprises determining whether the memory cell is in the lower resistance state, and if the memory cell is not in the lower resistance state then applying a second bias arrangement to the memory cell. The second bias arrangement comprises a second voltage pulse having a pulse height greater than that of the first voltage pulse.

摘要翻译： 这里描述了用于操作这样的设备的存储器件和方法。 本文描述了一种用于操作包括相变材料并且可编程为包括高电阻状态和较低电阻状态的多个电阻状态的存储单元的方法。 该方法包括将第一偏置装置施加到存储器单元以建立较低电阻状态，第一偏置装置包括第一电压脉冲。 该方法还包括确定存储器单元是处于较低电阻状态，以及如果存储单元不处于较低电阻状态，则向存储单元施加第二偏置布置。 第二偏置装置包括具有大于第一电压脉冲的脉冲高度的第二电压脉冲。

公开(公告)号：US20100221851A1

公开(公告)日：2010-09-02

申请号：US12777858

申请日：2010-05-11

申请人： Ming-Hsiu Lee ,  Chao-I Wu ,  Ming-Chang Kuo

发明人： Ming-Hsiu Lee ,  Chao-I Wu ,  Ming-Chang Kuo

IPC分类号： H01L21/66

CPC分类号： H01L22/34 ,  H01L2224/73204 ,  H01L2924/13091 ,  H01L2924/00

摘要： A semiconductor process test structure comprises an electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. Gate-induced drain leakage (GIDL) measurement techniques can then be used to characterize the charging status of the test structure.

摘要翻译： 半导体工艺测试结构包括电极，电荷俘获层和扩散区域。 测试结构是电容器状结构，其中电荷捕获层将在各种处理步骤期间捕获电荷。 然后可以使用栅极漏极泄漏（GIDL）测量技术来表征测试结构的充电状态。

公开(公告)号：US07652914B2

公开(公告)日：2010-01-26

申请号：US11651157

申请日：2007-01-09

申请人： Thomas Nirschl ,  Roger Cheek ,  Mark Lamorey ,  Ming-Hsiu Lee

发明人： Thomas Nirschl ,  Roger Cheek ,  Mark Lamorey ,  Ming-Hsiu Lee

IPC分类号： G11C11/00

CPC分类号： G11C13/003 ,  G11C13/0004 ,  G11C2213/74 ,  G11C2213/79

摘要： A memory includes a bit line and a phase change element. A first side of the phase change element is coupled to the bit line. The memory includes a first access device coupled to a second side of the phase change element and a second access device coupled to the second side of the phase change element. The memory includes a circuit for precharging the bit line and one of selecting only the first access device to program the phase change element to a first state and selecting both the first access device and the second access device to program the phase change element to a second state.

摘要翻译： 存储器包括位线和相变元件。 相变元件的第一侧耦合到位线。 存储器包括耦合到相变元件的第二侧的第一存取装置和耦合到相变元件的第二侧的第二存取装置。 存储器包括用于对位线进行预充电的电路和仅选择第一存取装置以将相变元件编程为第一状态的电路，并且选择第一存取装置和第二存取装置以将相变元件编程为第二 州。

公开(公告)号：US07626858B2

公开(公告)日：2009-12-01

申请号：US11450605

申请日：2006-06-09

申请人： Thomas Happ ,  Jan Boris Philipp ,  Ming-Hsiu Lee

发明人： Thomas Happ ,  Jan Boris Philipp ,  Ming-Hsiu Lee

IPC分类号： G11C11/00

CPC分类号： G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/79

摘要： A memory includes a phase change element having a first side and a second side and a first line coupled to the first side of the element. The memory includes an access device coupled to the second side of the element and a second line coupled to the access device for controlling the access device. The memory includes a circuit for precharging the first line to a first voltage and for applying a voltage pulse to the second line such that a current pulse is generated through the access device to the element to program the element to a selected one of more than two states. The voltage pulse has an amplitude based on the selected state.

摘要翻译： 存储器包括具有第一侧和第二侧以及耦合到元件的第一侧的第一线的相变元件。 存储器包括耦合到元件的第二侧的访问设备和耦合到访问设备的用于控制访问设备的第二行。 存储器包括用于将第一线路预充电到第一电压并且用于将电压脉冲施加到第二线路的电路，使得通过该接入装置向该元件生成电流脉冲以将该元件编程为多于两个中的所选择的一个 状态。 电压脉冲具有基于选择状态的幅度。

公开(公告)号：US07301219B2

公开(公告)日：2007-11-27

申请号：US11146777

申请日：2005-06-06

申请人： Tzu-Hsuan Hsu ,  Yen-Hao Shih ,  Ming-Hsiu Lee

发明人： Tzu-Hsuan Hsu ,  Yen-Hao Shih ,  Ming-Hsiu Lee

IPC分类号： H01L29/00 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L29/7885 ,  H01L29/7887 ,  H01L29/7923 ,  Y10S257/90

摘要： An asymmetrically doped memory cell has first and second N+ doped junctions on a P substrate. A composite charge trapping layer is disposed over the P substrate and between the first and the second N+ doped junctions. A N− doped region is positioned adjacent to the first N+ doped junction and under the composite charge trapping layer. A P− doped region is positioned adjacent to the second N+ doped junction and under the composite charge trapping layer. The asymmetrically doped memory cell will store charges at the end of the composite charge trapping layer that is above the P− doped region. The asymmetrically doped memory cell can function as an electrically erasable programmable read only memory cell, and is capable of multiple level cell operations. A method for making an asymmetrically doped memory cell is also described.

摘要翻译： 不对称掺杂的存储单元在P衬底上具有第一和第二N +掺杂结。 复合电荷捕获层设置在P衬底上并且在第一和第二N +掺杂结之间。 N掺杂区域邻近第一N +掺杂结并位于复合电荷俘获层下方。 P-掺杂区域邻近第二N +掺杂结并位于复合电荷俘获层下方。 非对称掺杂的存储单元将在复合电荷捕获层的末端在P掺杂区域之上存储电荷。 非对称掺杂的存储单元可以用作电可擦除可编程只读存储器单元，并且能够进行多级单元操作。 还描述了制造非对称掺杂的存储单元的方法。

公开(公告)号：US07209390B2

公开(公告)日：2007-04-24

申请号：US10876378

申请日：2004-06-24

申请人： Hang-Ting Lue ,  Yen-Hao Shih ,  Kuang Yeu Hsieh ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Tzu-Hsuan Hsu

发明人： Hang-Ting Lue ,  Yen-Hao Shih ,  Kuang Yeu Hsieh ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Tzu-Hsuan Hsu

IPC分类号： G11C16/00

CPC分类号： G11C16/3481 ,  G11C16/0466 ,  G11C16/3436

摘要： A memory cell with a charge trapping structure is programmed using refill cycles that include a program pulse followed by a charge balancing pulse that causes ejection of electrons from the charge trapping structure. The refill cycle causes a blue spectrum shift in the charge trap distribution in the charge trapping structure. The algorithm includes program verify operations after the program pulse, and completes when a successful program verify operation occurs after a number of refill cycles. The charge retention properties can be greatly improved by these refill cycles.

摘要翻译： 具有电荷俘获结构的存储单元使用包括编程脉冲，随后是电荷平衡脉冲的再填充循环被编程，该电荷平衡脉冲引起电荷从电荷捕获结构的喷出。 充电周期引起电荷捕获结构中电荷陷阱分布的蓝色光谱偏移。 该算法包括在程序脉冲之后的程序验证操作，并且在多个填充循环之后发生成功的程序验证操作时完成。 通过这些再填充循环可以大大提高电荷保持性。

公开(公告)号：US20070025153A1

公开(公告)日：2007-02-01

申请号：US11161359

申请日：2005-08-01

申请人： Chao-I Wu ,  Ming-Hsiu Lee

发明人： Chao-I Wu ,  Ming-Hsiu Lee

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C16/0475 ,  G11C16/18

摘要： A method of operating a non-volatile memory is provided, wherein the non-volatile memory at least includes: a gate structure formed by stacking a tunneling dielectric layer, charge trapping layer, a dielectric layer and a gate conducting layer sequentially, and a source region and a drain region. When the operating method is carried out, a ultraviolet is irradiated to the non-volatile memory to inject electrons into the charge trapping layer to erase the non-volatile memory, and a negative voltage is applied to the gate conductive layer and a positive voltage is applied to the drain region to program the non-volatile memory by band-to-band induced hot hole injection.

摘要翻译： 提供了一种操作非易失性存储器的方法，其中非易失性存储器至少包括：通过层叠隧穿介电层，电荷俘获层，电介质层和栅极导电层顺序地形成的栅极结构，以及源极 区域和漏极区域。 当执行操作方法时，紫外线照射到非易失性存储器以将电子注入电荷捕获层以擦除非易失性存储器，并且向栅极导电层施加负电压，并且正电压为 施加到漏极区域以通过频带带诱导的热空穴注入对非易失性存储器进行编程。