公开(公告)号：US5698881A

公开(公告)日：1997-12-16

申请号：US353240

申请日：1994-12-02

申请人： Takashi Yoshitomi ,  Masanobu Saito ,  Hisayo Momose ,  Hiroshi Iwai ,  Yukihiro Ushiku ,  Mizuki Ono ,  Yasushi Akasaka ,  Hideaki Nii ,  Satoshi Matsuda ,  Yasuhiro Katsumata ,  Tatsuya Ooguro ,  Claudio Fiegna

发明人： Takashi Yoshitomi ,  Masanobu Saito ,  Hisayo Momose ,  Hiroshi Iwai ,  Yukihiro Ushiku ,  Mizuki Ono ,  Yasushi Akasaka ,  Hideaki Nii ,  Satoshi Matsuda ,  Yasuhiro Katsumata ,  Tatsuya Ooguro ,  Claudio Fiegna

IPC分类号： H01L21/033 ,  H01L21/225 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/76

CPC分类号： H01L29/6659 ,  H01L21/0338 ,  H01L21/2255 ,  H01L21/28035 ,  H01L21/28123 ,  H01L21/823814 ,  H01L27/0928 ,  H01L29/0847 ,  H01L29/42376 ,  H01L29/66628

摘要： A MOS type semiconductor device has a gate whose length is 170 nm (0.17 .mu.m) or less, a junction depth of source and drain diffusion layers in the vicinity of a channel is 22 nm or less, and a concentration of impurities at the surface in the source and drain diffusion layers is made to 10.sup.20 cm.sup.-3 or more. Such structure is obtained using solid phase diffusion using heat range from 950.degree. C. to 1050.degree. C. and/or narrowing gate width by ashing or etching. The other MOS type semiconductor device is characterized in that the relationship between the junction depth x.sub.j �nm! in the source and drain diffusion layer regions and the effective channel length L.sub.eff �nm! is determined by L.sub.eff >0.69 x.sub.j -6.17.

摘要翻译： MOS型半导体器件具有长度为170nm（0.17μm）以下的栅极，沟道附近的源极和漏极扩散层的结深度为22nm以下，表面上的杂质浓度 在源极和漏极扩散层中形成1020cm-3以上。 这种结构使用从950℃到1050℃的热范围的固相扩散和/或通过灰化或蚀刻使栅极宽度变窄来获得。 其他MOS型半导体器件的特征在于源极和漏极扩散层区域中的结深度xj [nm]与有效沟道长度Leff [nm]之间的关系由Leff> 0.69×j-6.17确定。

公开(公告)号：US5237188A

公开(公告)日：1993-08-17

申请号：US798098

申请日：1991-11-27

申请人： Hiroshi Iwai ,  Toyota Morimoto ,  Hisayo S. Momose ,  Kikuo Yamabe ,  Yoshio Ozawa

发明人： Hiroshi Iwai ,  Toyota Morimoto ,  Hisayo S. Momose ,  Kikuo Yamabe ,  Yoshio Ozawa

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/51

CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66575 ,  H01L21/28211

摘要： A semiconductor device formed on a silicon substrate consisting of the steps of producing a silicon oxide film on the silicon substrate, producing a thin silicon nitride film on the silicon oxide film, thermally nitriding the silicon nitride film in an atmosphere of nitrogenous gas, producing a conductive film on the silicon nitride film nitrided in the atmosphere of the nitrogenous gas, producing a gate region from the silicon oxide film, the silicon nitride film, and the conductive film, a channel region being positioned under the gate region in the silicon substrate, producing a source region in the silicon substrate adjacent to one side of the channel region, producing a drain region in the silicon substrate adjacent to another side of the channel region, and producing wiring regions on the source region, the drain region, and the gate region.

摘要翻译： 一种形成在硅衬底上的半导体器件，包括在硅衬底上制造氧化硅膜的步骤，在氧化硅膜上产生薄氮化硅膜，在氮气气氛中对氮化硅膜进行氮化，产生 氮化硅膜上的导电膜在氮气气氛中氮化，从硅氧化膜，氮化硅膜和导电膜产生栅极区，沟道区位于硅衬底的栅极区下方， 在所述硅衬底中邻近所述沟道区的一侧产生源极区，在所述硅衬底中与所述沟道区的另一侧相邻的漏极区产生，并且在所述源极区，所述漏极区和所述栅极上产生布线区 地区。

公开(公告)号：US4881202A

公开(公告)日：1989-11-14

申请号：US138800

申请日：1987-12-29

申请人： Jun-ichi Tsujimoto ,  Masataka Matsui ,  Hiroshi Iwai ,  Takayuki Ohtani

发明人： Jun-ichi Tsujimoto ,  Masataka Matsui ,  Hiroshi Iwai ,  Takayuki Ohtani

IPC分类号： G11C11/401 ,  G11C11/408 ,  G11C29/00 ,  G11C29/04

CPC分类号： G11C29/802 ,  G11C29/844

摘要： In a semiconductor memory device with normal word lines and spare word lines, a partial decoder receives and decodes a predetermined two of the bit signals of the original logic levels of an address signal, and two of the bit signals of the complementary logic levels, which correspond to the predetermined two bit signals, and outputs different signal combinations of the predetermined two bit signals and the two corresponding bit signals. A spare word line selecting circuit receives the different signals and selects one of the different signals in order to select a spare word line which corresponds to a normal word line to which a defective cell is connected. The partial decoder may be used for both the normal word line selection and the selection of spare word lines. With a device constructed in such a manner, bit signals of an address signal are not directly input to the spare word line selecting circuit, but rather signals of different bit signal combinations are input to it. The spare word line selecting circuit merely selects signals of different combinations, and does not need the partial decoding of the address signal. Therefore, the chip area required for wiring may be remarkably reduced when compared with the conventional memory device.

公开(公告)号：US4872042A

公开(公告)日：1989-10-03

申请号：US630830

申请日：1984-07-13

申请人： Satoshi Maeda ,  Hiroshi Iwai

发明人： Satoshi Maeda ,  Hiroshi Iwai

IPC分类号： H01L27/02 ,  H01L27/108

CPC分类号： H01L27/0251 ,  H01L27/10805 ,  Y10S257/901

摘要： In a semiconductor device, a MOS transistor is formed in an island-like semiconductor region formed in a semiconductor substrate. The switching of the MOS transistor is controlled by changing a potential in the semiconductor region by means of a control circuit.

摘要翻译： 在半导体器件中，MOS晶体管形成在形成在半导体衬底中的岛状半导体区域中。 通过控制电路改变半导体区域中的电位来控制MOS晶体管的切换。

公开(公告)号：US4613230A

公开(公告)日：1986-09-23

申请号：US373629

申请日：1982-04-30

申请人： Hiroshi Iwai

发明人： Hiroshi Iwai

IPC分类号： G03F7/20 ,  G03B27/42 ,  G03B27/52 ,  G03B27/70

CPC分类号： G03F7/70541

摘要： A wafer exposure apparatus for covering the entire surface of a wafer with an array of desired chip patterns in a step and repeat process of projecting the desired chip pattern on a wafer by using a mask having the desired chip pattern. An alignment mark or chip specification mark is provided to a predetermined region of the wafer by a mask other than the mask having the desired chip pattern.

摘要翻译： 一种晶片曝光装置，用于在步骤中用期望的芯片图案的阵列覆盖晶片的整个表面，并且通过使用具有期望的芯片图案的掩模将期望的芯片图案投影在晶片上。 通过具有期望的芯片图案的掩模以外的掩模将对准标记或芯片规格标记提供给晶片的预定区域。

公开(公告)号：US4532696A

公开(公告)日：1985-08-06

申请号：US475944

申请日：1983-03-16

申请人： Hiroshi Iwai

发明人： Hiroshi Iwai

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/283 ,  H01L21/265

CPC分类号： H01L29/66621 ,  H01L21/76 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/76237

摘要： This invention provides a method of forming a buried element isolation region in a semiconductor substrate. The method comprises steps of forming a gate electrode material pattern on a gate insulating film formed on a semiconductive substrate, forming a gate electrode by selectively forming a groove in said gate electrode material pattern to thereby isolate said pattern and burying insulating material in the groove.

摘要翻译： 本发明提供一种在半导体衬底中形成掩埋元件隔离区的方法。 该方法包括以下步骤：在形成于半导体基板上的栅极绝缘膜上形成栅电极材料图案，通过在所述栅极电极材料图案中选择性地形成沟槽，形成栅电极，从而隔离所述图案并将绝缘材料埋入槽中。

公开(公告)号：US4523213A

公开(公告)日：1985-06-11

申请号：US396843

申请日：1982-07-09

申请人： Masami Konaka ,  Hiroshi Iwai ,  Yoshio Nishi

发明人： Masami Konaka ,  Hiroshi Iwai ,  Yoshio Nishi

IPC分类号： H01L21/316 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/00 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66772 ,  H01L21/26533 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/78 ,  H01L29/78654 ,  Y10S148/082

摘要： An MOS semiconductor device, wherein a buried region of silicon oxide or silicon nitride extends partly over the bottom plane of the channel region of an MOS transistor.

摘要翻译： 一种MOS半导体器件，其中氧化硅或氮化硅的掩埋区域部分地延伸到MOS晶体管的沟道区的底部平面上。

公开(公告)号：US4491486A

公开(公告)日：1985-01-01

申请号：US418802

申请日：1982-09-16

申请人： Hiroshi Iwai

发明人： Hiroshi Iwai

IPC分类号： H01L21/74 ,  H01L21/762 ,  H01L29/06 ,  H01L21/76

CPC分类号： H01L21/76237 ,  H01L21/743 ,  H01L21/76229 ,  H01L21/76232 ,  H01L29/0638

摘要： A method is proposed for manufacturing a semiconductor device, which comprises forming groove(s) having a vertical wall in a semiconductor substrate; doping the same type of impurity as that of the substrate at a dose of not less than 1.times.10.sup.14 cm.sup.-2 or the opposite type of impurity to that of the substrate in said groove(s) to form an impurity region; filling the groove(s) with an insulating material to form a field region. A semiconductor device having an impurity region of the same conductivity type as that of the semiconductor substrate under a buried field region and of a sheet resistance .rho.s=50 ohms/.quadrature. is also proposed.

摘要翻译： 提出一种用于制造半导体器件的方法，其包括在半导体衬底中形成具有垂直壁的沟槽; 以不小于1×10 14 cm -2的剂量掺杂相同类型的杂质或与所述沟槽中的衬底的相反类型的杂质掺杂以形成杂质区域; 用绝缘材料填充凹槽以形成场区域。 还提出了具有与掩埋场区域下的半导体衬底相同的导电类型的杂质区域和薄层电阻rho = 50欧姆/平方的半导体器件。

公开(公告)号：US4291137A

公开(公告)日：1981-09-22

申请号：US71795

申请日：1979-08-31

申请人： Yasushi Nakate ,  Hiroshi Iwai ,  Kiyoshi Nanishi

发明人： Yasushi Nakate ,  Hiroshi Iwai ,  Kiyoshi Nanishi

IPC分类号： C08L33/00 ,  C08G12/42 ,  C08L33/02 ,  C08L33/04 ,  C08L61/00 ,  C08L61/20 ,  C09D133/04 ,  C09D133/08 ,  C08L63/00

CPC分类号： C08G12/42 ,  C09D133/08 ,  C08L61/20

摘要： A one-pack high solid coating composition consisting essentially of (I) 100 parts by weight of an acrylic resin which is a copolymer having a glass transition temperature of -21.degree. to -50.degree. C. and a hydroxyl number of 40 to 280 and being prepared from (a) one or more members selected from hydroxyalkyl acrylates and methacrylates of the general formula ##STR1## wherein R is a hydrogen atom or a methyl group and R.sub.1 is a divalent alkyl group having 2 to 5 carbon atoms, and (b) one or more members selected from alkyl acrylates and methacrylates of the general formula ##STR2## wherein R is as defined above and R.sub.2 is a monovalent alkyl group having 1 to 12 carbon atoms, and glycidyl acrylates and methacrylates of the general formula ##STR3## wherein R is as defined above and R.sub.3 is a divalent alkyl group having 1 to 5 carbon atoms, (II) 20 to 160 parts by weight of an amino-formaldehyde resin etherified with a monohydric alcohol having 1 to 4 carbon atoms, and (III) 0.5 to 6 parts by weight, per 100 parts by weight of the total of the acrylic resin as component (I) and the etherified amino-formaldehyde resin as component (II) combined, of a blocked acid catalyst, said amount of the blocked acid catalyst being expressed in the amount of its acid.

摘要翻译： 一种单组分高固体涂料组合物，其基本上由（I）100重量份的丙烯酸树脂组成，该丙烯酸树脂是玻璃化转变温度为-21℃至-50℃，羟值为40至280的共聚物，以及 由（a）选自丙烯酸羟烷基酯和通式为“IMAGE”的甲基丙烯酸酯的一种或多种成分制备，其中R是氢原子或甲基，R 1是具有2至5个碳原子的二价烷基，和（b ）一种或多种选自通式“IMAGE”的丙烯酸烷基酯和甲基丙烯酸烷基酯的成员，其中R如上所定义，R 2是具有1至12个碳原子的一价烷基，以及通式为“IMAGE”的丙烯酸缩水甘油酯和甲基丙烯酸酯， 其中R如上定义，R 3是具有1至5个碳原子的二价烷基，（II）20至160重量份用醚化的具有1至4个碳原子的一元醇的氨基甲醛树脂和（III ）0.5〜6重量份， 作为组分（I）的丙烯酸树脂和作为组分（II）的醚化氨基甲醛树脂的合并的100重量份的封闭的酸催化剂，所述封闭的酸催化剂的量以 它的酸。

公开(公告)号：US08457582B2

公开(公告)日：2013-06-04

申请号：US12282954

申请日：2007-03-15

申请人： Atsushi Yamamoto ,  Koichi Ogawa ,  Hiroshi Iwai ,  Yoshio Koyanagi ,  Akira Kato

发明人： Atsushi Yamamoto ,  Koichi Ogawa ,  Hiroshi Iwai ,  Yoshio Koyanagi ,  Akira Kato

IPC分类号： H04B1/06

CPC分类号： H04B7/0851

摘要： In the adaptive control apparatus, a computation unit computes weighting coefficients, using a first adaptive control method in a proportion α of a first computation amount, where the first adaptive control method has a first convergence rate and a first convergence error. Further, a computation unit computes weighting coefficients from initial values of the weighting coefficients computed by the computation unit, using a second adaptive control method in a proportion (1−α) of a second computation amount, where the second adaptive control method has a second convergence rate slower than the first convergence rate and a second convergence error smaller than the first convergence error. A controller controls determination of a ratio α/(1-α) based on a moving speed of a mobile unit, and controls the computation units to perform computing processes.

摘要翻译： 在自适应控制装置中，计算单元使用第一自适应控制方法具有第一收敛速度和第一收敛误差的第一计算量的比例α来使用第一自适应控制方法来计算加权系数。 此外，计算单元使用第二自适应控制方法以第二计算量的比例（1-α）计算由计算单元计算的加权系数的初始值的加权系数，其中第二自适应控制方法具有第二 收敛速度比第一收敛速度慢，第二收敛误差小于第一收敛误差。 控制器基于移动单元的移动速度来控制α/（1-α）比率的确定，并且控制计算单元执行计算处理。