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    MICROELECTRONIC ASSEMBLIES WITH THROUGH DIE ATTACH FILM CONNECTIONS
    71.
    发明申请
    MICROELECTRONIC ASSEMBLIES WITH THROUGH DIE ATTACH FILM CONNECTIONS 有权

    公开(公告)号：US20230087367A1

    公开(公告)日：2023-03-23

    申请号：US17481506

    申请日：2021-09-22

    Applicant: Intel Corporation

    Inventor： Xiaoxuan Sun ,  Omkar G. Karhade ,  Dingying Xu ,  Sairam Agraharam ,  Xavier Francois Brun

    IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/538 ,  H01L23/31

    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface with first conductive contacts and an opposing second surface with second conductive contacts, in a first layer; a die attach film (DAF), at the first surface of the first die, including through-DAF vias (TDVs), wherein respective ones of the TDVs are electrically coupled to respective ones of the first conductive contacts; a conductive pillar in the first layer; and a second die, in a second layer on the first layer, wherein the second die is electrically coupled to the second conductive contacts on the second surface of the first die and electrically coupled to the conductive pillar.

    Method and materials for warpage thermal and interconnect solutions
    76.
    发明授权
    Method and materials for warpage thermal and interconnect solutions 审中-公开

    公开(公告)号：US10672626B2

    公开(公告)日：2020-06-02

    申请号：US15469284

    申请日：2017-03-24

    Applicant: Intel Corporation

    Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Aditya S. Vaidya ,  Nachiket R. Raravikar ,  Eric J. Li

    IPC: H01L21/56 ,  H01L21/768 ,  H01L21/78 ,  H01L23/498 ,  H01L25/10 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31

    Abstract: Embodiments describe a semiconductor package that includes a substrate, a die bonded to the substrate, and a solder paste overmold layer formed over a top surface of the die. In an embodiment, the solder paste comprises a high-melting point metal, a solder matrix, intermetallic compounds and a polymer. The overmold layer has a high elastic modulus, a coefficient of thermal expansion similar to the substrate, and reduces the warpage of the package. In an embodiment, interconnects of a semiconductor package are formed with a no-slump solder paste that includes vents. Vents may be formed through a conductive network formed by the high-melting point metal, solder matrix and intermetallic compounds. In an embodiment, vents provide a path through the interconnect that allows for moisture outgassing. In an embodiment, a mold layer may be mechanically anchored to the interconnects by the vents, thereby providing improved mechanical continuity to the mold layer.

    Warpage control for microelectronics packages
    78.
    发明授权
    Warpage control for microelectronics packages 有权

    公开(公告)号：US10256198B2

    公开(公告)日：2019-04-09

    申请号：US15468067

    申请日：2017-03-23

    Applicant: INTEL CORPORATION

    Inventor： Eric J. Li ,  Guotao Wang ,  Huiyang Fei ,  Sairam Agraharam ,  Omkar G. Karhade ,  Nitin A. Deshpande

    IPC: H01L23/12 ,  H01L23/053 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H05K3/30 ,  H05K3/34 ,  H01L21/48 ,  H05K1/18

    Abstract: Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package.

    THERMAL INTERFACES FOR INTEGRATED CIRCUIT PACKAGES
    79.
    发明申请
    THERMAL INTERFACES FOR INTEGRATED CIRCUIT PACKAGES 审中-公开

    公开(公告)号：US20180090411A1

    公开(公告)日：2018-03-29

    申请号：US15279222

    申请日：2016-09-28

    Applicant: Intel Corporation

    Inventor： Edvin Cetegen ,  Omkar G. Karhade ,  Kedar Dhane ,  Chandra M. Jha

    IPC: H01L23/367 ,  H01L23/373

    CPC classification number: H01L23/3736 ,  H01L23/3733 ,  H01L23/42 ,  H01L23/4275 ,  H01L23/433

    Abstract: A thermal interface may include a wired network made of a first TIM, and a second TIM surrounding the wired network. A heat spreader lid may include a wired network attached to an inner surface of the heat spreader lid. An IC package may include a heat spreader lid placed over a first electronic component and a second electronic component. A first thermal interface may be formed between the first electronic component and the inner surface of the heat spreader lid, and a second thermal interface may be formed between the second electronic component and the inner surface of the heat spreader lid. The first thermal interface may include a wired network of a first TIM surrounded by a second TIM, while the second thermal interface may include the second TIM, without a wired network of the first TIM. Other embodiments may be described and/or claimed.

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