公开(公告)号：US20170243784A1

公开(公告)日：2017-08-24

申请号：US15422923

申请日：2017-02-02

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Cheng Chi ,  Ruilong Xie

IPC: H01L21/768 ,  H01L29/51 ,  H01L29/45 ,  H01L29/06

CPC classification number: H01L21/76837 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76883 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/456 ,  H01L29/517

Abstract: Techniques relate to forming an integrated circuit. Trench contacts are formed on top of at least one source and drain of an intermediate structure. An interlayer dielectric is formed on top of the intermediate structure. A trench is cut through the interlayer dielectric, through at least one of the trench contacts, down to a shallow trench isolation area. The trench is filled with a filling material. Upper contacts are formed on top of the trench contacts in the interlayer dielectric. A first metal layer pattern is patterned such that a separation is formed by a filling material width of the filling material. First metal layers are formed according to the first metal layer pattern, where tips of the first metal layers are aligned to the filling material that fills the trench, such that the tips of the first metal layers are separated by the filling material width.

公开(公告)号：US09589847B1

公开(公告)日：2017-03-07

申请号：US15046916

申请日：2016-02-18

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Cheng Chi ,  Ruilong Xie

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/06 ,  H01L23/535 ,  H01L27/02

CPC classification number: H01L21/76837 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76883 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/456 ,  H01L29/517

Abstract: Techniques relate to forming an integrated circuit. Trench contacts are formed on top of at least one source and drain of an intermediate structure. An interlayer dielectric is formed on top of the intermediate structure. A trench is cut through the interlayer dielectric, through at least one of the trench contacts, down to a shallow trench isolation area. The trench is filled with a filling material. Upper contacts are formed on top of the trench contacts in the interlayer dielectric. A first metal layer pattern is patterned such that a separation is formed by a filling material width of the filling material. First metal layers are formed according to the first metal layer pattern, where tips of the first metal layers are aligned to the filling material that fills the trench, such that the tips of the first metal layers are separated by the filling material width.

Abstract translation: 技术涉及形成集成电路。 沟槽触点形成在中间结构的至少一个源极和漏极的顶部上。 在中间结构的顶部形成层间电介质。 沟槽穿过层间电介质，通过至少一个沟槽触点切割到浅沟槽隔离区域。 沟槽填充有填充材料。 上部触点形成在层间电介质中的沟槽触点的顶部。 图案化第一金属层图案，使得通过填充材料的填充材料宽度形成分离。 根据第一金属层图案形成第一金属层，其中第一金属层的末端与填充沟槽的填充材料对准，使得第一金属层的末端被填充材料宽度分开。

公开(公告)号：US20160336225A1

公开(公告)日：2016-11-17

申请号：US14710894

申请日：2015-05-13

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES, INC. ,  STMicroelectronics, Inc.

Inventor： Shyng-Tsong Chen ,  Cheng Chi ,  Chi-Chun Liu ,  Sylvie M. Mignot ,  Yann A. Mignot ,  Hosadurga K. Shobha ,  Terry A. Spooner ,  Wenhui Wang ,  Yongan Xu

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/535

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329

Abstract: A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.

Abstract translation: 提供了形成通孔到半导体器件的下层的方法。 该方法可以包括使用侧壁图像转移过程在下层上形成柱。 介电层形成在柱和下层之上; 以及图案化在所述电介质层上的通孔掩模，所述通孔掩模具有至少部分地与所述支柱重叠的掩模开口。 使用通孔掩模在电介质层中蚀刻通孔开口，掩模开口在第一方向上限定通孔开口的第一横向尺寸，并且柱沿不同于第一方向的第二方向限定通孔开口的第二横向尺寸 方向。 通孔开口填充有导体以形成通孔。 还提供了半导体器件和通孔结构。

公开(公告)号：US20250132293A1

公开(公告)日：2025-04-24

申请号：US18382471

申请日：2023-10-20

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Tao Li ,  Joshua M. Rubin ,  Cheng Chi

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B12/00

Abstract: A memory device and formation thereof. The memory device includes a stack of memory dies. Each memory die in the stack of memory dies includes two or more layers of memory devices.

公开(公告)号：US12057387B2

公开(公告)日：2024-08-06

申请号：US17110381

申请日：2020-12-03

Applicant: International Business Machines Corporation

Inventor： Reinaldo Vega ,  David Wolpert ,  Takashi Ando ,  Praneet Adusumilli ,  Cheng Chi

IPC: H01L23/522 ,  H01L23/528 ,  H01L29/423 ,  H01L29/66 ,  H01L29/94 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L23/5226 ,  H01L23/5286 ,  H01L28/55 ,  H01L29/4236 ,  H01L29/66181 ,  H01L29/945

Abstract: An approach to forming a semiconductor device where the semiconductor device includes a first power rail with one or more vertically stacked contact vias connecting to the first power rail to a portion of a first de-coupling capacitor. The semiconductor device includes the first de-coupling capacitor in a first portion of a semiconductor substrate in a first gate cut trench.

公开(公告)号：US20230123883A1

公开(公告)日：2023-04-20

申请号：US17485333

申请日：2021-09-25

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Julien Frougier ,  Kangguo Cheng ,  Chanro Park ,  Cheng Chi ,  Jinning Liu

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor structure comprises a substrate defining a first axis and a second axis orthogonal to the first axis, a first nanosheet region disposed on the substrate and defining a first channel width along the second axis, a first gate disposed around the first nanosheet region, a second nanosheet region disposed on the substrate and defining a second channel width along the second axis less than the first channel width of the first nanosheet region and a second gate disposed around the second nanosheet region.

公开(公告)号：US20230093462A1

公开(公告)日：2023-03-23

申请号：US17482874

申请日：2021-09-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Reinaldo Vega ,  Takashi Ando ,  Cheng Chi ,  Praneet Adusumilli

IPC: H01L23/522 ,  H01L23/528

Abstract: A field effect device is provided. The field effect device includes an active gate structure, a gate contact within the active gate structure, wherein the gate contact is the same height as the active gate structure, and a gate cut dielectric on opposite sides of the gate contact and active gate structure.

公开(公告)号：US11508823B2

公开(公告)日：2022-11-22

申请号：US17132980

申请日：2020-12-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Ekmini Anuja De Silva ,  Jing Guo ,  Hao Tang ,  Cheng Chi

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786 ,  H01L29/08 ,  H01L21/265 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51

Abstract: A field effect transistor is provided. The field effect transistor includes a first source/drain on a substrate, a second source/drain on the substrate, and a channel region between the first source/drain and the second source/drain. The field effect transistor further includes a metal liner on at least three sides of the first source/drain and/or the second source/drain, wherein the metal liner covers less than the full length of a sidewall of the first source/drain and/or the second source/drain. The field effect transistor further includes a metal-silicide between the metal liner and the first source/drain and/or the second source/drain, and a conductive contact on the metal liner on the first source/drain and/or the second source/drain, wherein the conductive contact is a conductive material different from the conductive material of the metal liner.

公开(公告)号：US11456416B2

公开(公告)日：2022-09-27

申请号：US16952234

申请日：2020-11-19

Applicant: International Business Machines Corporation

Inventor： Praneet Adusumilli ,  Takashi Ando ,  Reinaldo Vega ,  Cheng Chi

IPC: H01L45/00 ,  H01L27/24 ,  G06N3/08

Abstract: A resistive random access memory (ReRAM) device is provided. The ReRAM device includes a stack structure including a first electrode, a metal oxide layer in contact with the first electrode, and a second electrode in contact with the metal oxide layer. A portion of the stack structure is modified by ion implantation, and the modified portion of the stack structure is offset from edges of the stack structure.

公开(公告)号：US20220293853A1

公开(公告)日：2022-09-15

申请号：US17198775

申请日：2021-03-11

Applicant: International Business Machines Corporation

Inventor： Praneet Adusumilli ,  Takashi Ando ,  REINALDO VEGA ,  Cheng Chi

IPC: H01L45/00 ,  G11C13/00

Abstract: A device includes an electronic component, and the electronic component includes a first pad, a second pad, and a strip connecting the first pad and the second pad. The device further includes a first electrode in contact with the first pad and a second electrode in contact with the second pad. The electronic component is made of a phase change material. At least one of the first electrode and the second electrode is coated with a material that is configured to increase a difference in workfunction between the first electrode and the second electrode.