公开(公告)号：US10411120B2

公开(公告)日：2019-09-10

申请号：US15654896

申请日：2017-07-20

Applicant: International Business Machines Corporation

Inventor： Robin Hsin-Kuo Chao ,  Michael A. Guillorn ,  Chi-Chun Liu ,  Shogo Mochizuki ,  Chun W. Yeung

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/306 ,  H01L21/265 ,  H01L29/08

Abstract: A method for manufacturing a semiconductor device includes forming a stacked configuration of first and second semiconductor layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a second semiconductor layer stacked on a first semiconductor layer, forming a plurality of dummy gates spaced apart from each other on the stacked configuration, wherein the plurality of dummy gates cover a portion of the stacked configuration in a channel region, performing an implantation of a semiconductor material on exposed portions of the stacked configuration in a source/drain region, wherein the implantation increases a concentration of the semiconductor material in the exposed portions of the stacked configuration, and selectively removing first semiconductor layers having an increased concentration of the semiconductor material from the source/drain region, wherein the removed first semiconductor layers correspond in position to the first semiconductor layers in the channel region.

公开(公告)号：US20190273127A1

公开(公告)日：2019-09-05

申请号：US15911626

申请日：2018-03-05

Applicant: International Business Machines Corporation

Inventor： Peng Xu ,  Kangguo Cheng ,  Xuefeng Liu ,  Chi-Chun Liu ,  Yongan Xu

IPC: H01L49/02 ,  H01L21/3105

Abstract: Techniques for generating enhanced inductors and other electronic devices are presented. A device generator component (DGC) performs directed-self assembly (DSA) co-polymer deposition on a circular guide pattern formed in low-k dielectric film, and DSA annealing to form two polymers in the form of alternating concentric rings; performs a loop cut in the concentric rings to form concentric segments; fills the cut portion with insulator material; selectively removes first polymer, fills the space with low-k dielectric, and planarizes the surface; selectively removes the second polymer, fills the space with conductive material, and planarizes the surface; deposits low-k film on top of the concentric segments and insulator material that filled the loop cut portion; forms vias in the low-k film, wherein each via spans from an end of one segment to an end of another segment; and fills vias with conductive material to form conductive connectors to form substantially spiral conductive structure.

公开(公告)号：US20190237562A1

公开(公告)日：2019-08-01

申请号：US15886539

申请日：2018-02-01

Applicant: international Business Machines Corporation

Inventor： Chi-Chun Liu ,  Chun Wing Yeung ,  Robin Hsin Kuo Chao ,  Zhenxing Bi ,  Kristin Schmidt ,  Yann Mignot

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/3105 ,  H01L29/40 ,  H01L29/423

Abstract: Techniques for VFET gate length control are provided. In one aspect, a method of forming a VFET device includes: patterning fins in a substrate; forming first polymer spacers alongside opposite sidewalls of the fins; forming second polymer spacers offset from the fins by the first polymer spacers; removing the first polymer spacers selective to the second polymer spacers; reflowing the second polymer spacers to close a gap to the fins; forming a cladding layer above the second polymer spacers; removing the second polymer spacers; forming gates along opposite sidewalls of the fins exposed in between the bottom spacers and the cladding layer, wherein the gates have a gate length Lg set by removal of the second polymer spacers; forming top spacers above the cladding layer; and forming top source and drains above the top spacers. A VFET device is also provided.

公开(公告)号：US10312103B2

公开(公告)日：2019-06-04

申请号：US15445112

申请日：2017-02-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sean D. Burns ,  Nelson M. Felix ,  Chi-Chun Liu ,  Yann A. M. Mignot ,  Stuart A. Sieg

IPC: H01L21/308 ,  H01L21/3065 ,  H01L29/66

Abstract: A method for forming fins includes forming a three-color hardmask fin pattern on a fin base layer. The three-color hardmask fin pattern has hardmask fins of three mutually selectively etchable compositions. A region on the three-color hardmask fin pattern is masked, leaving one or more fins of a first color exposed. All exposed fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color. The mask and all fins of a second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.

公开(公告)号：US20190140052A1

公开(公告)日：2019-05-09

申请号：US16233825

申请日：2018-12-27

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Cheng Chi ,  Chi-Chun Liu ,  Ruilong Xie ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/7827

Abstract: Techniques for VFET top source and drain epitaxy are provided. In one aspect, a method of forming a VFET includes: patterning a fin to form a bottom source/drain region and a fin channel of the VFET; forming bottom spacers on the bottom source/drain region; depositing a high-κ gate dielectric onto the bottom spacers and along sidewalls of the fin channel; forming gates over the bottom spacers; forming top spacers on the gates; partially recessing the fin channel to create a trench between the top spacers; forming a nitride liner along sidewalls of the trench; fully recessing the fin channel through the trench such that side portions of the fin channel remain intact; and forming a doped epitaxial top source and drain region over the fin channel. Methods not requiring a nitride liner and VFET formed using the present techniques are also provided.

公开(公告)号：US10256289B2

公开(公告)日：2019-04-09

申请号：US15805829

申请日：2017-11-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kisup Chung ,  Isabel C. Estrada-Raygoza ,  Hemanth Jagannathan ,  Chi-Chun Liu ,  Yann A. M. Mignot ,  Hao Tang

IPC: H01L49/02

Abstract: Methods of forming capacitors include forming a self-assembled pattern of periodic first and second domains using first and second block copolymer materials over a substrate. The second block copolymer material is etched away. Material from the substrate is etched based on a pattern defined by the first block copolymer material to form cavities in the substrate. A capacitor stack is conformally deposited over the substrate, such that the capacitor stack is formed on horizontal surfaces of the substrate and vertical surfaces of the cavities.

公开(公告)号：US20190101829A1

公开(公告)日：2019-04-04

申请号：US15719608

申请日：2017-09-29

Applicant: International Business Machines Corporation

Inventor： Indira P. Seshadri ,  Ekmini Anuja De Silva ,  Chi-Chun Liu ,  Cheng Chi ,  Jing Guo ,  Luciana Meli Thompson

IPC: G03F7/11 ,  G03F7/16

Abstract: Embodiments of the present invention provide systems and methods for trapping amines. This in turn mitigates the undesired scumming and footing effects in a photoresist. The polymer brush is grafted onto a silicon nitride surface. The functional groups and molecular weight of the polymer brush provide protons and impose steric hindrance, respectively, to trap amines diffusing from a silicon nitride surface.

公开(公告)号：US20190080958A1

公开(公告)日：2019-03-14

申请号：US15703097

申请日：2017-09-13

Applicant: International Business Machines Corporation

Inventor： Cheng Chi ,  Kafai Lai ,  Chi-Chun Liu ,  Yongan Xu

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76816 ,  H01L21/02118 ,  H01L21/02356 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/76897

Abstract: A method of forming an interconnect element includes forming a trench in a dielectric material. The trench has a width equal to twice a natural pitch of a block copolymer. The block copolymer includes a first polymer and a second polymer. The method includes filling the trench with the block copolymer.

公开(公告)号：US10157789B2

公开(公告)日：2018-12-18

申请号：US15239178

申请日：2016-08-17

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES, INC. ,  STMicroelectronics, Inc.

Inventor： Shyng-Tsong Chen ,  Cheng Chi ,  Chi-Chun Liu ,  Sylvie M. Mignot ,  Yann A. Mignot ,  Hosadurga K. Shobha ,  Terry A. Spooner ,  Wenhui Wang ,  Yongan Xu

IPC: H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.

公开(公告)号：US20180082850A1

公开(公告)日：2018-03-22

申请号：US15813518

申请日：2017-11-15

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Cheng Chi ,  Chi-Chun Liu ,  Peng Xu

IPC: H01L21/308 ,  H01L21/311

CPC classification number: H01L21/3085 ,  H01L21/0337 ,  H01L21/31116 ,  H01L29/66795 ,  H01L29/6681

Abstract: A method of forming a semiconductor device and resulting structures having a dummy semiconductor fin removed from within an array of tight pitch semiconductor fins by forming a first spacer including a first material on a substrate; forming a second spacer including a second material on the substrate, the second spacer adjacent to the first spacer; and applying an etch process to the first spacer and the second spacer; wherein the etch process removes the first spacer at a first etch rate; wherein the etch process removes the second spacer at a second etch rate; wherein the first etch rate is different than the second etch rate.