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    Techniques for forming replacement metal gate for VFET
    71.
    发明授权
    Techniques for forming replacement metal gate for VFET 有权

    公开(公告)号：US11437489B2

    公开(公告)日：2022-09-06

    申请号：US16585403

    申请日：2019-09-27

    Applicant: International Business Machines Corporation

    Inventor： Ruilong Xie ,  Heng Wu ,  Chanro Park ,  Kangguo Cheng

    IPC: H01L29/165 ,  H01L29/66 ,  H01L29/267 ,  H01L29/78 ,  H01L29/08 ,  H01L21/8234 ,  H01L27/088

    Abstract: RMG techniques for VFET formation using a chamfering process are provided. In one aspect, a method of forming a VFET device includes: patterning fins adjacent to one another in a substrate; forming bottom source/drains at a base of the fins; forming bottom spacers over the bottom source/drains; forming sacrificial gates alongside the fins; forming top source/drains at a top of the fins; forming top spacers surrounding the top source/drains; removing the sacrificial gates; depositing a high-κ gate dielectric along sidewalls of the fins; removing the high-κ gate dielectric from an opening between adjacent top spacers; depositing at least a first workfunction-setting metal layer onto the high-κ gate dielectric; removing the first workfunction-setting metal layer from the opening between the adjacent top spacers; and depositing at least a second workfunction-setting metal layer onto the first workfunction-setting metal layer to form replacement metal gates. A VFET device is also provided.

    Inverse T-shaped contact structures having air gap spacers
    74.
    发明授权
    Inverse T-shaped contact structures having air gap spacers 有权

    公开(公告)号：US11362193B2

    公开(公告)日：2022-06-14

    申请号：US16662446

    申请日：2019-10-24

    Applicant: International Business Machines Corporation

    Inventor： Kangguo Cheng ,  Choonghyun Lee ,  Juntao Li ,  Heng Wu ,  Peng Xu

    IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78

    Abstract: A method of fabricating air gap spacers is provided. The method includes forming gate structures to extend upwardly from a substrate with source or drain (S/D) regions disposed between the gate structures and with contact trenches defined above the S/D regions and between the gate structures. The method further includes disposing contacts in the contact trenches. The method also includes configuring the contacts to define open-ended air gap spacer trenches with the gate structures. In addition, the method includes forming a cap over the open-ended air gap spacer trenches to define the open-ended air gap spacer trenches as air gap spacers. The gate structures have an initial structure prior to and following the disposing and the configuring of the contacts and prior to and following the forming of the cap.

    BOTTOM SOURCE/DRAIN FOR FIN FIELD EFFECT TRANSISTORS
    75.
    发明申请
    BOTTOM SOURCE/DRAIN FOR FIN FIELD EFFECT TRANSISTORS 有权

    公开(公告)号：US20220173240A1

    公开(公告)日：2022-06-02

    申请号：US17671080

    申请日：2022-02-14

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Heng Wu ,  Shogo Mochizuki ,  Gen Tsutsui ,  Kangguo Cheng

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/24

    Abstract: A method of forming a vertical transport fin field effect transistor device is provided. The method includes forming vertical fins on a substrate, depositing a protective liner on the sidewalls of the vertical fins, and removing a portion of the substrate to form a support pillar beneath at least one of the vertical fins. The method further includes etching a cavity in the support pillar of the at least one of the vertical fins, and removing an additional portion of the substrate to form a plinth beneath the support pillar of the vertical fin. The method further includes growing a bottom source/drain layer on the substrate adjacent to the plinth, and forming a diffusion plug in the cavity, wherein the diffusion plug is configured to block diffusion of dopants from the bottom source/drain layer above a necked region in the support pillar.

    Bottom source/drain for fin field effect transistors
    76.
    发明授权
    Bottom source/drain for fin field effect transistors 有权

    公开(公告)号：US11276781B2

    公开(公告)日：2022-03-15

    申请号：US16849101

    申请日：2020-04-15

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Heng Wu ,  Shogo Mochizuki ,  Gen Tsutsui ,  Kangguo Cheng

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/24

    Abstract: A method of forming a vertical transport fin field effect transistor device is provided. The method includes forming vertical fins on a substrate, depositing a protective liner on the sidewalls of the vertical fins, and removing a portion of the substrate to form a support pillar beneath at least one of the vertical fins. The method further includes etching a cavity in the support pillar of the at least one of the vertical fins, and removing an additional portion of the substrate to form a plinth beneath the support pillar of the vertical fin. The method further includes growing a bottom source/drain layer on the substrate adjacent to the plinth, and forming a diffusion plug in the cavity, wherein the diffusion plug is configured to block diffusion of dopants from the bottom source/drain layer above a necked region in the support pillar.

    Formation of air gap spacers for reducing parasitic capacitance
    78.
    发明授权
    Formation of air gap spacers for reducing parasitic capacitance 有权

    公开(公告)号：US11183577B2

    公开(公告)日：2021-11-23

    申请号：US16738383

    申请日：2020-01-09

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Kangguo Cheng ,  Peng Xu ,  Choonghyun Lee ,  Heng Wu

    IPC: H01L29/49 ,  H01L21/768 ,  H01L29/66 ,  H01L23/522 ,  H01L29/08

    Abstract: A method is presented for reducing parasitic capacitance. The method includes forming a source region and a drain region within a substrate, forming spacers in direct contact with sidewalls of a sacrificial layer, depositing an inter-layer dielectric (ILD) over the source and drain regions, replacing the sacrificial layer with a gate structure, removing the ILD, and depositing a sacrificial dielectric layer. The method further includes removing portions of the sacrificial dielectric layer to expose top surfaces of the source and drain regions, depositing a conductive material over the exposed top surfaces of the source and drain regions, and removing remaining portions of the sacrificial dielectric layer to form air gap spacers between the gate structure and the source and drain regions.

    Stacked nanosheet CFET with gate all around structure
    79.
    发明授权
    Stacked nanosheet CFET with gate all around structure 有权

    公开(公告)号：US11177258B2

    公开(公告)日：2021-11-16

    申请号：US16798316

    申请日：2020-02-22

    Applicant: International Business Machines Corporation

    Inventor： Ruilong Xie ,  Alexander Reznicek ,  Heng Wu ,  Lan Yu

    IPC: H01L29/66 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/786 ,  H01L27/092 ,  H01L29/49 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/28

    Abstract: CFET devices having a gate-all-around structure are provided. In one aspect, a method of forming a CFET device includes: forming a nanosheet device stack(s) on a substrate including alternating first/second nanosheets of a first/second material, wherein lower nanosheets in the nanosheet device stack(s) are separated from the substrate and from upper nanosheets in the nanosheet device stack(s) by sacrificial nanosheets; forming a ζ-shaped dielectric spacer separating the lower and upper nanosheets; forming lower/upper source and drains on opposite sides of the lower/upper nanosheets, separated by an isolation spacer; selectively removing the first nanosheets; and forming a first gate surrounding a portion of each of the lower nanosheets including a first workfunction-setting metal(s), and a second gate surrounding a portion of each of the upper nanosheets including a second workfunction-setting metal(s), wherein the first and second workfunction-setting metals are separated by the ζ-shaped dielectric spacer. A CFET device is also provided.

    Stacked upper fin and lower fin transistor with separate gate
    80.
    发明授权
    Stacked upper fin and lower fin transistor with separate gate 有权

    公开(公告)号：US11164870B2

    公开(公告)日：2021-11-02

    申请号：US16580720

    申请日：2019-09-24

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Heng Wu ,  Ruilong Xie ,  Chun Wing Yeung ,  Lan Yu

    IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165

    Abstract: Forming a first opening in a first double stacked fin and forming a second opening in a second double stacked fin, by removing a high silicon germanium layer, forming a low k spacer, removing a dummy gate, and removing portions of the low k spacer from an outer surface of the first double stacked fin, and an outer surface of the second double stacked fin. A structure including an upper fin of a double stacked fin separated from a lower fin of a double stacked fin by a low k spacer and by a p type field effect transistor work function metal layer (PFET WFM), where a horizontal lower surface of the upper fin is coplanar with a horizontal upper surface of the low k spacer and a horizontal lower surface of the low k spacer is coplanar with a horizontal upper surface of the PFET WFM.

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