公开(公告)号：US11908907B2

公开(公告)日：2024-02-20

申请号：US17118853

申请日：2020-12-11

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Heng Wu ,  Ruilong Xie ,  Tian Shen ,  Kai Zhao

IPC分类号： H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/45 ,  H01L29/66

CPC分类号： H01L29/41741 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/45 ,  H01L29/66666 ,  H01L29/7827

摘要： An embodiment of the invention may include a Vertical Field Effect Transistor (VFET) structure, and method of making that structure, having a first VFET and a second VFET. The first VFET may include a single liner between a first source/drain epi and a contact. The second VFET may include two liners between a second source/drain epi and a contact. This may enable proper contact liner matching for differing VFET devices.

公开(公告)号：US20230343833A1

公开(公告)日：2023-10-26

申请号：US17728469

申请日：2022-04-25

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Liqiao Qin ,  Heng Wu ,  Ruilong Xie ,  Tian Shen

IPC分类号： H01L29/24 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/10

CPC分类号： H01L29/24 ,  H01L27/092 ,  H01L21/823807 ,  H01L21/823871 ,  H01L21/823885 ,  H01L29/1037 ,  H01L29/401

摘要： A semiconductor device including a semiconductor substrate, a lower metal contact disposed upon the semiconductor substrate, a gate structure disposed upon the lower metal contact, an upper metal contact disposed upon the gate structure, and a plurality of semiconductor carriers disposed in contact with both the lower metal contact and the upper metal contact, the plurality of semiconductor carriers disposed in channels passing through the gate structure.

公开(公告)号：US12108692B2

公开(公告)日：2024-10-01

申请号：US17473359

申请日：2021-09-13

申请人： International Business Machines Corporation

发明人： Heng Wu ,  Tian Shen ,  Kevin W. Brew ,  Jingyun Zhang

IPC分类号： H10N70/20 ,  H10N70/00

CPC分类号： H10N70/253 ,  H10N70/063 ,  H10N70/231 ,  H10N70/823 ,  H10N70/8413 ,  H10N70/8828

摘要： A phase change memory, a system, and a method to prevent high resistance drift within a phase change memory through a phase change memory cell with three terminals and self-aligned metal contacts. The phase change memory may include a bottom electrode. The phase change memory may also include a heater proximately connected to the bottom electrode. The phase change memory may also include a phase change material proximately connected to the heater. The phase change memory may also include metal proximately connected to at least two sides of the phase change material. The phase change memory may also include three terminals, where a bottom terminal is located at an area proximately connected to the heater and two top terminals are located at areas proximately connected to the metal.

公开(公告)号：US20230081603A1

公开(公告)日：2023-03-16

申请号：US17473359

申请日：2021-09-13

申请人： International Business Machines Corporation

发明人： Heng Wu ,  Tian Shen ,  Kevin W. Brew ,  Jingyun Zhang

IPC分类号： H01L45/00

摘要： A phase change memory, a system, and a method to prevent high resistance drift within a phase change memory through a phase change memory cell with three terminals and self-aligned metal contacts. The phase change memory may include a bottom electrode. The phase change memory may also include a heater proximately connected to the bottom electrode. The phase change memory may also include a phase change material proximately connected to the heater. The phase change memory may also include metal proximately connected to at least two sides of the phase change material. The phase change memory may also include three terminals, where a bottom terminal is located at an area proximately connected to the heater and two top terminals are located at areas proximately connected to the metal.

公开(公告)号：US11380843B2

公开(公告)日：2022-07-05

申请号：US16789502

申请日：2020-02-13

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Tian Shen ,  Heng Wu ,  Kevin W. Brew ,  Jingyun Zhang

IPC分类号： H01L45/00

摘要： A method is presented for improved linearity of a phase change memory (PCM) cell structure. The method includes forming a bottom electrode over a substrate, constructing a PCM stack including a plurality of PCM layers each having a different crystallization temperature over the bottom electrode, and forming a top electrode over the PCM stack. The crystallization temperature varies in an ascending order from the bottom electrode to the top electrode.

公开(公告)号：US20210257547A1

公开(公告)日：2021-08-19

申请号：US16789502

申请日：2020-02-13

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Tian Shen ,  Heng Wu ,  Kevin W. Brew ,  Jingyun Zhang

IPC分类号： H01L45/00

摘要： A method is presented for improved linearity of a phase change memory (PCM) cell structure. The method includes forming a bottom electrode over a substrate, constructing a PCM stack including a plurality of PCM layers each having a different crystallization temperature over the bottom electrode, and forming a top electrode over the PCM stack. The crystallization temperature varies in an ascending order from the bottom electrode to the top electrode.

公开(公告)号：US20240113200A1

公开(公告)日：2024-04-04

申请号：US17960116

申请日：2022-10-04

申请人： International Business Machines Corporation

发明人： HUIMEI ZHOU ,  MIAOMIAO WANG ,  Julien Frougier ,  Andrew M. Greene ,  Barry Paul Linder ,  Kai Zhao ,  Ruilong Xie ,  Tian Shen ,  Veeraraghavan S. Basker

IPC分类号： H01L29/66 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08

CPC分类号： H01L29/66553 ,  H01L21/76831 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/66545

摘要： An integrated circuit apparatus includes a substrate and a well contact that is disposed on the substrate. The well contact includes first and second source/drain structures that are disposed on the substrate; a metal vertical portion that contacts the substrate immediately between the first and second source/drain structures; inner spacers that electrically insulate the vertical portion from the adjacent source/drain structures; bottom dielectric isolation that electrically insulates the source/drain structures from the substrate; and a well portion that is embedded into the substrate in registry with the vertical portion. The well portion is doped differently than the substrate.

公开(公告)号：US20230206964A1

公开(公告)日：2023-06-29

申请号：US17565137

申请日：2021-12-29

申请人： International Business Machines Corporation

发明人： Tian Shen ,  Kevin W. Brew ,  Heng Wu

IPC分类号： G11C7/10 ,  G11C7/12 ,  G11C7/16 ,  G11C8/08 ,  G06F17/16

CPC分类号： G11C7/1012 ,  G11C7/12 ,  G11C7/16 ,  G11C8/08 ,  G11C7/1063 ,  G11C7/109 ,  G06F17/16

摘要： A plurality of bit lines corresponding to elements of an input vector intersect a plurality of word lines and a plurality of memristive cells are located at the intersections. At least three cells are grouped together to represent a single matrix element. At least three word lines correspond to each element of an output vector. An A/D converter is coupled to each of the word lines, and for each line, except a first, in each group, a shifter has an input coupled to one of the A/D converters. For each group, an addition-subtraction block adds the output of the A/D converter coupled to the first one of the word lines to outputs of each of the shifters except that for a last one of the word lines, subtracts the output of the last shifter, and outputs a corresponding element of an output vector.

公开(公告)号：US11316105B2

公开(公告)日：2022-04-26

申请号：US16821660

申请日：2020-03-17

申请人： International Business Machines Corporation

发明人： Tian Shen ,  Ruilong Xie ,  Kevin W. Brew ,  Heng Wu ,  Jingyun Zhang

IPC分类号： H01L45/00

摘要： A phase change material switch includes a phase change layer disposed on a metal liner. A gate dielectric layer is disposed on the phase change layer. A metal gate liner is disposed on the gate dielectric layer.

公开(公告)号：US11101213B2

公开(公告)日：2021-08-24

申请号：US16774893

申请日：2020-01-28

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Baozhen Li ,  Chih-Chao Yang ,  Jim Shih-Chun Liang ,  Tian Shen

IPC分类号： H01L23/525 ,  H01L23/522 ,  H01L23/528

摘要： An eFuse structure including a semiconductor substrate; back end of the line (BEOL) metallization levels on the semiconductor substrate; vias extending through the metallization levels; at least one of the metallization levels including one or more metallic plates in electrical contact with one of the vias, the one or more metallic plates having at least one fusible link in electrical contact with one or more additional vias. The eFuse structure may form a multi-fuse structure such that each fusible link may be fused separately or together at the same time.