公开(公告)号：US11107814B2

公开(公告)日：2021-08-31

申请号：US16847451

申请日：2020-04-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Junli Wang ,  Michael P. Belyansky

IPC: H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8234

Abstract: A method of forming a fin field effect transistor complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a plurality of multilayer fin templates and vertical fins on a substrate, wherein one multilayer fin template is on each of the plurality of vertical fins. The method further includes forming a dummy gate layer on the substrate, the plurality of vertical fins, and the multilayer fin templates, and removing a portion of the dummy gate layer from the substrate from between adjacent pairs of the vertical fins. The method further includes forming a fill layer between adjacent pairs of the vertical fins. The method further includes removing a portion of the dummy gate layer from between the fill layer and the vertical fins, and forming a sidewall spacer layer on the fill layer and between the fill layer and the vertical fins.

公开(公告)号：US10985075B2

公开(公告)日：2021-04-20

申请号：US16157325

申请日：2018-10-11

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Unoh Kwon ,  Vijay Narayanan

IPC: H01L21/8238 ,  H01L29/49 ,  H01L27/092 ,  H01L21/28

Abstract: Embodiments of the invention are directed to a method that includes forming a first channel fin in an n-type region of a substrate, forming a second channel fin in a p-type region of the substrate, and depositing a gate dielectric over the substrate and the first and second channel fins. A work function metal stack is deposited over the gate dielectric, the first fin in the n-type region, and the second fin in the p-type region. The work function metal stack over the gate dielectric and the first fin in the n-type region forms a first work function metal stack. The work function metal stack over the gate dielectric and the second fin in the p-type region forms a second work function metal stack. The first work function metal stack includes at least one shared layer of work function metal that is shared with the second work function metal stack.

公开(公告)号：US20210111068A1

公开(公告)日：2021-04-15

申请号：US17131998

申请日：2020-12-23

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Dechao Guo ,  Junli Wang ,  Ruqiang Bao

IPC: H01L21/768 ,  H01L27/092 ,  H01L23/535 ,  H01L23/532 ,  H01L21/8238 ,  H01L29/66

Abstract: Embodiments of the invention are directed to an integrated circuit. A non-limiting example of the integrated circuit includes a transistor formed over a substrate. A dielectric region is formed over the transistor and the substrate. A trench is positioned in the dielectric region and over a S/D region of the transistor. A first liner and a conductive plug are within the trench such that the first liner and the conductive plug are only present within a bottom portion of the trench. A substantially oxygen-free replacement liner and a S/D contact are within the top portion of the trench such that a bottom contact surface of the S/D contact directly couples to a top surface of the conductive plug.

公开(公告)号：US10790199B2

公开(公告)日：2020-09-29

申请号：US16371621

申请日：2019-04-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Hemanth Jagannathan ,  Choonghyun Lee ,  Richard G. Southwick

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/10 ,  H01L29/78 ,  H01L27/092 ,  H01L21/02 ,  H01L21/311 ,  H01L21/324 ,  H01L29/161

Abstract: A method of forming fin structures that includes providing at least one silicon germanium containing fin structure, and forming a fin liner on the at least one silicon germanium containing fin structure. The fin liner includes a silicon germanium and oxygen containing layer. The method continues with annealing the at least on silicon germanium containing fin structure having the fin liner present thereon. During the annealing, the silicon germanium oxygen containing layer reacts with the silicon germanium containing fin structure to provide surface formation of a silicon rich layer on the silicon germanium containing fin structure.

公开(公告)号：US10777659B2

公开(公告)日：2020-09-15

申请号：US16191549

申请日：2018-11-15

Applicant: International Business Machines Corporation

Inventor： Choonghyun Lee ,  Ruqiang Bao ,  Shogo Mochizuki ,  Brent A. Anderson ,  Hemanth Jagannathan

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/786 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/04 ,  H01L29/423 ,  H01L29/49 ,  H01L29/16

Abstract: A semiconductor device and a method for fabricating the same. The semiconductor device includes at least a n-type vertical FET and a p-type vertical FET. The n-type vertical FET includes at least a first bottom source/drain layer. The p-type vertical FET includes at least a second bottom source/drain layer. A silicon dioxide layer separates the first bottom source/drain layer and the second bottom source/drain layer. The method includes forming a first bottom source/drain layer in a p-type vertical FET device area. A germanium dioxide layer is formed in contact with the first semiconductor layer a second semiconductor fin formed within a n-type vertical FET device area. A silicon dioxide layer is formed in contact with the first bottom source/drain layer from the germanium dioxide layer. A second bottom source/drain layer is formed in contact with the second semiconductor fin and the silicon dioxide layer.

公开(公告)号：US10777469B2

公开(公告)日：2020-09-15

申请号：US16157786

申请日：2018-10-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Junli Wang ,  Brent A. Anderson ,  Xin Miao

IPC: H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/225 ,  H01L27/092 ,  H01L21/762 ,  H01L29/78

Abstract: Semiconductor devices and methods of forming the same include forming a doped dielectric layer on a semiconductor fin. The doped dielectric layer is annealed to drive dopants from the doped dielectric layer into the semiconductor fin. A gate stack is formed on the semiconductor fin.

公开(公告)号：US10741663B1

公开(公告)日：2020-08-11

申请号：US16374732

申请日：2019-04-03

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Hemanth Jagannathan ,  Michael P. Belyansky

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/16 ,  H01L27/092 ,  H01L21/28 ,  H01L21/8238

Abstract: A vertical transport field-effect transistor includes gate metal protected by a conformal encapsulation layer. Techniques for fabricating the transistor include depositing the conformal encapsulation layer over the gate metal prior to depositing an additional encapsulation layer such as a nitride layer. The conformal encapsulation layer protects the gate metal during deposition of the additional encapsulation layer, thereby avoiding oxidation or nitridation of the gate metal. The conformal encapsulation layer may be an amorphous silicon layer deposited at relatively low temperature.

公开(公告)号：US20200235008A1

公开(公告)日：2020-07-23

申请号：US16252763

申请日：2019-01-21

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Dechao Guo ,  Junli Wang ,  Ruqiang Bao

IPC: H01L21/768 ,  H01L27/092 ,  H01L23/535 ,  H01L23/532 ,  H01L21/8238

Abstract: Embodiments of the invention are directed to a method of forming an interconnect structure. A non-limiting example of the method includes forming a transistor over a substrate, forming a dielectric region over the transistor and the substrate, and forming a trench positioned in the dielectric region and over a source or drain (S/D) region of the transistor, wherein a sidewall of the trench includes a gate spacer of the transistor. A volume of the trench is increased by removing the gate spacer from the sidewall of the trench. A first liner and a conductive plug are deposited within a bottom portion of the trench.

公开(公告)号：US20200212220A1

公开(公告)日：2020-07-02

申请号：US16813105

申请日：2020-03-09

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Brent A. Anderson ,  ChoongHyun Lee ,  Hemanth Jagannathan

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/423

Abstract: A semiconductor structure includes a substrate, a bottom source/drain region disposed on a top surface of the substrate, and a plurality of fins disposed over a top surface of the bottom source/drain region. The fins provide vertical transport channels for one or more vertical transport field-effect transistors. The semiconductor structure also includes at least one self-aligned shared contact disposed between an adjacent pair of the plurality of fins. The adjacent pair of the plurality of fins includes a first fin providing a first vertical transport channel for a first vertical transport field-effect transistor and a second fin providing a second vertical transport channel for a second vertical transport field-effect transistor.

公开(公告)号：US20200211908A1

公开(公告)日：2020-07-02

申请号：US16813196

申请日：2020-03-09

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Hemanth Jagannathan ,  Brent A. Anderson ,  ChoongHyun Lee

IPC: H01L21/8238 ,  H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L23/535 ,  H01L27/092 ,  H01L29/08 ,  H01L29/49

Abstract: A method of forming a semiconductor structure includes forming a plurality of fins over a top surface of a bottom source/drain region disposed over a top surface of a substrate, the fins providing vertical transport channels for a plurality of vertical transport field-effect transistors. The method also includes forming a first gate conductor surrounding a first one of an adjacent pair of the plurality of fins providing a first vertical transport channel for a first vertical transport field-effect transistor, forming a second gate conductor surrounding a second one of the adjacent pair of the plurality of fins providing a second vertical transport channel for a second vertical transport field-effect transistor, and forming at least one shared gate contact to the first gate conductor and the second gate conductor, the at least one shared gate contact being formed at first ends of the adjacent pair of the plurality of fins.