公开(公告)号：US20230395596A1

公开(公告)日：2023-12-07

申请号：US17805039

申请日：2022-06-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Su Chen Fan ,  Dominik Metzler ,  Hemanth Jagannathan ,  Jing Guo ,  Jay William Strane ,  Ruilong Xie

IPC: H01L27/088 ,  H01L27/12 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L27/088 ,  H01L27/124 ,  H01L27/1248 ,  H01L23/5329 ,  H01L23/5226

Abstract: A semiconductor structure including a dielectric isolation region between and electrical isolating a first top contact of a first stacked transistor from a second top contact of a second stacked transistor, where at least one vertical surface of the first top contact is substantially flush with at least one vertical surface of the isolation region, and where at least one vertical surface of the second top contact is substantially flush with the at least one vertical surface of the isolation region.

公开(公告)号：US11742354B2

公开(公告)日：2023-08-29

申请号：US17482426

申请日：2021-09-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Christopher J Waskiewicz ,  Alexander Reznicek ,  Su Chen Fan ,  Heng Wu

IPC: H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes first and second vertical transport field-effect transistor (VTFET) devices. Each of the first and second VTFET devices includes a bottom epitaxial layer, a plurality of channel fins formed on the bottom epitaxial layer, a first interlayer dielectric (ILD) layer formed between the channel fins, a high-κ metal gate formed between the channel fins and the first ILD layer, a top epitaxial layer formed discretely on each of the channel fins, and a trench epitaxial layer formed continuously across the top epitaxial layer, a portion of the first ILD layer also being formed between the first and second VTFET device. The semiconductor device also includes a second ILD layer formed on the portion of the first ILD layer that is between the first and second VTFET devices, the second ILD layer separating the top epitaxial layers of the first and second VTFET devices.

公开(公告)号：US20230145135A1

公开(公告)日：2023-05-11

申请号：US17520812

申请日：2021-11-08

Applicant: International Business Machines Corporation

Inventor： Yann Mignot ,  Su Chen Fan ,  Jing Guo ,  Lijuan Zou

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/8234

CPC classification number: H01L29/66795 ,  H01L29/7851 ,  H01L29/0847 ,  H01L21/823431 ,  H01L21/823418 ,  H01L21/823468 ,  H01L29/6656

Abstract: Techniques for area scaling of contacts in VTFET devices are provided. In one aspect, a VTFET device includes: a fin(s); a bottom source/drain region at a base of the fin(s); a gate stack alongside the fin(s); a top source/drain region present at a top of the fin(s); a bottom source/drain contact to the bottom source/drain region; and a gate contact to the gate stack, wherein the bottom source drain and gate contacts each includes a top portion having a width W1CONTACT over a bottom portion having a width W2CONTACT, wherein W2CONTACT

公开(公告)号：US20230124681A1

公开(公告)日：2023-04-20

申请号：US17504765

申请日：2021-10-19

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Su Chen Fan ,  Veeraraghavan S. Basker ,  Julien Frougier ,  Nicolas Loubet

IPC: H01L27/092 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L21/8238 ,  H01L29/417

Abstract: A CMOS (complementary metal-oxide semiconductor) device includes an n-channel metal-oxide semiconductor (NMOS) device, a p-channel metal-oxide semiconductor (PMOS) device, the NMOS and the PMOS device surrounded by a first dielectric material, the NMOS device separated from the PMOS device by a second dielectric material, a first NMOS gate separated from a first PMOS gate by the second dielectric material, a second NMOS gate electrically connected to a second PMOS gate by a metal link disposed between the NMOS gate and the PMOS gate, the metal link disposed above the second dielectric material, a first source/drain (S/D) contact disposed above the second dielectric material, the first S/D contact disposed in contact with both NMOS S/D region and a PMOS S/D region, and a second S/D contact disposed adjacent to the second dielectric material, the second S/D contact disposed in contact with a single S/D region.

公开(公告)号：US11621199B2

公开(公告)日：2023-04-04

申请号：US17458777

申请日：2021-08-27

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Su Chen Fan ,  Ruilong Xie ,  Huai Huang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/45 ,  H01L29/78 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66 ,  H01L21/285

Abstract: A method for manufacturing a semiconductor device includes forming a first vertical transistor structure in a first device region on a substrate, and forming a second vertical transistor structure in a second device region on the substrate. The first vertical transistor structure includes a first plurality of fins, and the second vertical transistor structure includes a second plurality of fins. A plurality of first source/drain regions are grown from upper portions of the first plurality of fins, and a contact liner layer is formed on the first source/drain regions. The method further includes forming a plurality of first silicide portions from the contact liner layer on the first source/drain regions, and forming a plurality of second silicide portions on a plurality of second source/drain regions extending from upper portions of the second plurality of fins. The second silicide portions have a different composition than the first silicide portions.

公开(公告)号：US20210391224A1

公开(公告)日：2021-12-16

申请号：US17458777

申请日：2021-08-27

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Su Chen Fan ,  Ruilong Xie ,  Huai Huang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/45 ,  H01L29/78 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66 ,  H01L21/285

Abstract: A method for manufacturing a semiconductor device includes forming a first vertical transistor structure in a first device region on a substrate, and forming a second vertical transistor structure in a second device region on the substrate. The first vertical transistor structure includes a first plurality of fins, and the second vertical transistor structure includes a second plurality of fins. A plurality of first source/drain regions are grown from upper portions of the first plurality of fins, and a contact liner layer is formed on the first source/drain regions. The method further includes forming a plurality of first silicide portions from the contact liner layer on the first source/drain regions, and forming a plurality of second silicide portions on a plurality of second source/drain regions extending from upper portions of the second plurality of fins. The second silicide portions have a different composition than the first silicide portions.

公开(公告)号：US11183593B2

公开(公告)日：2021-11-23

申请号：US16592389

申请日：2019-10-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Huimei Zhou ,  Su Chen Fan ,  Shogo Mochizuki ,  Peng Xu ,  Nicolas J. Loubet

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L27/06 ,  H01L29/08

Abstract: A method of forming stacked fin field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first semiconductor layer on a surface of the substrate, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, a separation layer on the third semiconductor layer, a fourth semiconductor layer on the separation layer, a fifth semiconductor layer on the fourth semiconductor layer, and a sixth semiconductor layer on the fifth semiconductor layer. The method further includes forming a plurality of channels through the layer stack to the surface of the substrate, and removing portions of the second semiconductor layer and fifth semiconductor layer to form lateral grooves.

公开(公告)号：US11011417B2

公开(公告)日：2021-05-18

申请号：US16428008

申请日：2019-05-31

Applicant: International Business Machines Corporation

Inventor： Su Chen Fan ,  Ruilong Xie ,  Andrew Greene ,  Veeraraghavan S. Basker

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L21/02

Abstract: A method includes applying a first dielectric material onto a semiconductor substrate to form a first dielectric layer on the semiconductor substrate, creating a plurality of openings in the dielectric layer, depositing a sacrificial material within the openings of the dielectric layer, removing the sacrificial material from at least a first segment of a first trench of the openings, depositing a second dielectric fill material into the first segment of the first trench opening where the sacrificial material was removed, removing the sacrificial material from at least some of the remaining openings and depositing a metallic material within the first trench opening to define at least first and second lines in the first trench and form a metallic interconnect structure.

公开(公告)号：US10957552B2

公开(公告)日：2021-03-23

申请号：US16666948

申请日：2019-10-29

Applicant: International Business Machines Corporation

Inventor： Yongan Xu ,  Ekmini Anuja De Silva ,  Su Chen Fan ,  Yann Mignot

IPC: H01L21/308 ,  G03F1/22 ,  H01L21/033

Abstract: Semiconductor structures fabricated via extreme ultraviolet (EUV) lithographic patterning techniques implementing directional deposition on a EUV resist mask improves selectivity and critical dimension control during the patterning of features in multiple layers of the semiconductor substrate. A semiconductor structure includes a substrate structure having an extreme ultraviolet resist mask disposed over one or more additional layers of the substrate structure. The extreme ultraviolet resist mask defines patterning features. A hard mask layer including a hard mask material is disposed on the extreme ultraviolet resist mask and covers the patterning features of the extreme ultraviolet resist mask.

公开(公告)号：US20210005735A1

公开(公告)日：2021-01-07

申请号：US17026451

申请日：2020-09-21

Applicant: International Business Machines Corporation

Inventor： Christopher J. Waskiewicz ,  Su Chen Fan ,  Hari Prasad Amanapu ,  Hemanth Jagannathan

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/768 ,  H01L29/78

Abstract: A semiconductor includes a semiconductor substrate having a bottom source/drain region and a vertical semiconductor fin having a bottom end that contacts the semiconductor substrate. The semiconductor device further includes a top source/drain region on a top end of the vertical semiconductor. The top source/drain region is separated from the semiconductor substrate by the vertical semiconductor fin. The semiconductor device further includes an electrically conductive cap on an outer surface of the top source/drain region.