公开(公告)号：US20110199972A1

公开(公告)日：2011-08-18

申请号：US13026777

申请日：2011-02-14

申请人： Nirmal Chindhu Warke ,  Srinath Hosur ,  Martin J. Izzard ,  Siraj Akhtar ,  Baher S. Haroun ,  Marco Corsi

发明人： Nirmal Chindhu Warke ,  Srinath Hosur ,  Martin J. Izzard ,  Siraj Akhtar ,  Baher S. Haroun ,  Marco Corsi

IPC分类号： H04W40/00

CPC分类号： H04W40/00 ,  H01Q3/26 ,  H01Q9/20 ,  H01Q21/0006 ,  H01Q21/0037 ,  H04B7/0617 ,  H04B17/336 ,  H04L45/74 ,  H04L49/3009 ,  H04L49/40 ,  H04W40/06 ,  H04W40/12 ,  Y02D70/00 ,  Y02D70/166 ,  Y02D70/322 ,  Y02D70/34

摘要： Embodiments of the invention provide a system and method for chip to chip communications in electronic circuits. A router or switch receives data packets at input port ASICs. A routing table on the input port ASIC or on a routing ASIC is used to identify a destination port ASIC based upon header information in the data packet. The data packet is transmitted from the input port ASIC to the destination port ASIC using millimeter wave signals that are transmitted across a waveguide or a wireless interface.

摘要翻译： 本发明的实施例提供了一种用于电子电路中芯片到芯片通信的系统和方法。 路由器或交换机在输入端口ASIC处接收数据包。 输入端口ASIC或路由ASIC上的路由表用于根据数据包中的报头信息识别目标端口ASIC。 使用在波导或无线接口上传输的毫米波信号，将数据分组从输入端口ASIC发送到目标端口ASIC。

公开(公告)号：US07962813B2

公开(公告)日：2011-06-14

申请号：US12434929

申请日：2009-05-04

申请人： Lee D. Whetsel ,  Baher S. Haroun ,  Brian J. Lasher ,  Anjali Kinra

发明人： Lee D. Whetsel ,  Baher S. Haroun ,  Brian J. Lasher ,  Anjali Kinra

IPC分类号： G01R31/28

CPC分类号： G01R31/3177 ,  G01R31/31727 ,  G01R31/318555

摘要： IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.

摘要翻译： IEEE 1149.1测试接入端口（TAP）可用于IC和知识产权核心设计级别。 TAP用作用于访问IC和核心内的各种嵌入式电路的串行通信端口，包括： IEEE 1149.1边界扫描电路，内置测试电路，内部扫描电路，IEEE 1149.4混合信号测试电路，IEEE P5001在线仿真电路和IEEE P1532系统编程电路。 可选择地访问IC内的TAP是理想的，因为在许多情况下，仅能够访问期望的TAP导致在IC内可以执行测试，仿真和编程的方式的改进。 描述了一种TAP链接模块，其允许使用1149.1指令扫描操作来选择性地访问嵌入在IC内的TAP。

公开(公告)号：US20110084864A1

公开(公告)日：2011-04-14

申请号：US12577075

申请日：2009-10-09

申请人： Ganesh K. Balachandran ,  Baher S. Haroun

发明人： Ganesh K. Balachandran ,  Baher S. Haroun

IPC分类号： H03M1/66

CPC分类号： H03C5/00 ,  H03D7/1441 ,  H03D7/1458 ,  H03D2200/0023

摘要： An embodiment of the invention provides a single-ended polar transmitting circuit. The single-ended polar transmitting circuit comprises a DAC, a differential-to-single-ended converter, a GmC filter and a load. The GmC filter comprises two gain stages, two filters, two switching devices, a translinear loop and a current mirror. When a second clock signal is high, a first current is conducted through the load, a second switching device and a second gain stage. When a first clock signal is high, a second current is conducted through a first switching device and the second gain stage. The first gain stage has a transconductance Gm1 and the second gain stage has a transconductance Gm2. The bandwidth of the GmC filter is approximately equal to the square root of the quantity (Gm1*Gm2)/(C1*C2). The bandwidth of the GmC filter is substantially a constant value.

摘要翻译： 本发明的实施例提供了一种单端极性发射电路。 单端极性发射电路包括DAC，差分到单端转换器，GmC滤波器和负载。 GmC滤波器包括两个增益级，两个滤波器，两个开关器件，一个跨线回路和一个电流镜。 当第二时钟信号为高时，通过负载，第二开关装置和第二增益级传导第一电流。 当第一时钟信号为高时，通过第一开关器件和第二增益级传导第二电流。 第一增益级具有跨导Gm1，第二增益级具有跨导Gm2。 GmC滤波器的带宽近似等于量的平方根（Gm1 * Gm2）/（C1 * C2）。 GmC滤波器的带宽基本上是一个恒定值。

公开(公告)号：US20100197053A1

公开(公告)日：2010-08-05

申请号：US12761544

申请日：2010-04-16

申请人： Baher S. Haroun ,  Gaurav Chandra ,  Vijaya Bhaskar Rentala ,  Venkatesh Srinivasan ,  Hisashi Shichijo ,  Krishnaswamy Nagaraj

发明人： Baher S. Haroun ,  Gaurav Chandra ,  Vijaya Bhaskar Rentala ,  Venkatesh Srinivasan ,  Hisashi Shichijo ,  Krishnaswamy Nagaraj

IPC分类号： H01L21/66

CPC分类号： H03M3/35 ,  H01L22/34 ,  H03M3/43 ,  H03M3/438

摘要： In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defeats are within an allowable range.

摘要翻译： 在用于监测晶片中的缺陷的装置和方法中，在每个晶片的区域上制造监视电路。 监测电路包括代表位于晶片的管芯区域中的类似器件的代表性器件。 如果存在于代表性装置中的缺陷有助于产生噪声，从而导致在所选代表装置中可测量的差分信号的不平衡。 使用共模电压作为参考来测量不平衡的数字化电路将差分信号数字化为数字信号，数字信号表示由缺陷产生的噪声。 数字信号以可配置的时间间隔存储以形成数字比特流。 将数字比特流与参考进行比较，以确定失败是否在允许的范围内。

公开(公告)号：US07546502B2

公开(公告)日：2009-06-09

申请号：US12117207

申请日：2008-05-08

申请人： Lee D. Whetsel ,  Baher S. Haroun ,  Brian J. Lasher ,  Anjali Kinra

发明人： Lee D. Whetsel ,  Baher S. Haroun ,  Brian J. Lasher ,  Anjali Kinra

IPC分类号： G01R31/28

CPC分类号： G01R31/3177 ,  G01R31/31727 ,  G01R31/318555

摘要： IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.

摘要翻译： IEEE 1149.1测试接入端口（TAP）可用于IC和知识产权核心设计级别。 TAP用作用于访问IC和核心内的各种嵌入式电路的串行通信端口，包括： IEEE 1149.1边界扫描电路，内置测试电路，内部扫描电路，IEEE 1149.4混合信号测试电路，IEEE P5001在线仿真电路和IEEE P1532系统编程电路。 可选择地访问IC内的TAP是理想的，因为在许多情况下，仅能够访问期望的TAP导致在IC内可以执行测试，仿真和编程的方式的改进。 描述了一种TAP链接模块，其允许使用1149.1指令扫描操作来选择性地访问嵌入在IC内的TAP。

公开(公告)号：US20090057889A1

公开(公告)日：2009-03-05

申请号：US12048294

申请日：2008-03-14

申请人： Rajen M. Murugan ,  Robert F. McCarthy ,  Baher S. Haroun ,  Peter R. Harper

发明人： Rajen M. Murugan ,  Robert F. McCarthy ,  Baher S. Haroun ,  Peter R. Harper

IPC分类号： H01L23/48 ,  H01L21/20 ,  H01L21/44

CPC分类号： H01L23/3114 ,  H01L23/5223 ,  H01L23/525 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/02313 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/16 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19104

摘要： One aspect of the invention provides a semiconductor device that includes a microchip having an outermost surface. First and second bond pads are located on the microchip and near the outermost surface. A first UBM contact is located on the outermost surface and between the first and second bond pads. The first UBM contact is offset from the first bond pad. A second UBM contact is located on the outermost surface and between the first and second bond pads. The second UBM contact is offset from the second bond pad, and a capacitor supported by the microchip is located between the first and second UBM contacts.

摘要翻译： 本发明的一个方面提供一种包括具有最外表面的微芯片的半导体器件。 第一和第二接合焊盘位于微芯片上并且在最外表面附近。 第一UBM触点位于最外表面和第一和第二接合焊盘之间。 第一个UBM触点与第一个焊盘相抵消。 第二UBM触点位于最外表面上以及第一和第二接合焊盘之间。 第二UBM触点偏离第二接合焊盘，并且由微芯片支撑的电容器位于第一和第二UBM触点之间。

公开(公告)号：US20080215282A1

公开(公告)日：2008-09-04

申请号：US12117207

申请日：2008-05-08

申请人： Lee D. Whetsel ,  Baher S. Haroun ,  Brian J. Lasher ,  Anjali Kinra

发明人： Lee D. Whetsel ,  Baher S. Haroun ,  Brian J. Lasher ,  Anjali Kinra

IPC分类号： G01R31/317 ,  G01R31/02

CPC分类号： G01R31/3177 ,  G01R31/31727 ,  G01R31/318555

摘要： IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.

摘要翻译： IEEE 1149.1测试接入端口（TAP）可用于IC和知识产权核心设计级别。 TAP用作用于访问IC和核心内的各种嵌入式电路的串行通信端口，包括： IEEE 1149.1边界扫描电路，内置测试电路，内部扫描电路，IEEE 1149.4混合信号测试电路，IEEE P5001在线仿真电路和IEEE P1532系统编程电路。 可选择地访问IC内的TAP是理想的，因为在许多情况下，仅能够访问期望的TAP导致在IC内可以执行测试，仿真和编程的方式的改进。 描述了一种TAP链接模块，其允许使用1149.1指令扫描操作来选择性地访问嵌入在IC内的TAP。

公开(公告)号：US07389456B2

公开(公告)日：2008-06-17

申请号：US11279503

申请日：2006-04-12

申请人： Lee D. Whetsel ,  Baher S. Haroun ,  Brian J. Lasher ,  Anjali Kinra

发明人： Lee D. Whetsel ,  Baher S. Haroun ,  Brian J. Lasher ,  Anjali Kinra

IPC分类号： G01R31/28

CPC分类号： G01R31/3177 ,  G01R31/31727 ,  G01R31/318555

摘要： IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.

摘要翻译： IEEE 1149.1测试接入端口（TAP）可用于IC和知识产权核心设计级别。 TAP用作用于访问IC和核心内的各种嵌入式电路的串行通信端口，包括： IEEE 1149.1边界扫描电路，内置测试电路，内部扫描电路，IEEE 1149.4混合信号测试电路，IEEE P5001在线仿真电路和IEEE P1532系统编程电路。 可选择地访问IC内的TAP是理想的，因为在许多情况下，仅能够访问期望的TAP导致在IC内可以执行测试，仿真和编程的方式的改进。 描述了一种TAP链接模块，其允许使用1149.1指令扫描操作来选择性地访问嵌入在IC内的TAP。

公开(公告)号：US07058862B2

公开(公告)日：2006-06-06

申请号：US09864509

申请日：2001-05-24

申请人： Lee D. Whetsel ,  Baher S. Haroun ,  Brian J. Lasher ,  Anjali Kinra

发明人： Lee D. Whetsel ,  Baher S. Haroun ,  Brian J. Lasher ,  Anjali Kinra

IPC分类号： G01R31/28

CPC分类号： G01R31/3177 ,  G01R31/31727 ,  G01R31/318555

摘要： IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.

摘要翻译： IEEE 1149.1测试接入端口（TAP）可用于IC和知识产权核心设计级别。 TAP用作用于访问IC和核心内的各种嵌入式电路的串行通信端口，包括： IEEE 1149.1边界扫描电路，内置测试电路，内部扫描电路，IEEE 1149.4混合信号测试电路，IEEE P5001在线仿真电路和IEEE P1532系统编程电路。 可选择地访问IC内的TAP是理想的，因为在许多情况下，仅能够访问期望的TAP导致在IC内可以执行测试，仿真和编程的方式的改进。 描述了一种TAP链接模块，其允许使用1149.1指令扫描操作来选择性地访问嵌入在IC内的TAP。

公开(公告)号：US06798296B2

公开(公告)日：2004-09-28

申请号：US10292225

申请日：2002-11-12

申请人： Heng-Chih Lin ,  Baher S. Haroun ,  Tiang Tun Foo

发明人： Heng-Chih Lin ,  Baher S. Haroun ,  Tiang Tun Foo

IPC分类号： H03L700

CPC分类号： H03K3/0322 ,  H03K5/1252 ,  H03L7/089 ,  H03L7/093 ,  H03L7/18 ,  H03L2207/50

摘要： A wide band, wide operating range, general purpose digital phase locked loop (PLL) runs in the digital domain except for the associated Time Digitizer (T2D) and Digitally-Controlled-Oscillator (DCO). By calibrating the T2D and DCO on the fly, a constant PLL loop BW is achieved by using the calibrated Phase Frequency Detection (PFD) and DCO information to normalize the control loop correction regardless of the input clock frequency, power supply voltage, processing and temperature variations. PLL loop BW is completely decoupled from the operating conditions and semiconductor device variation. This means that the PLL loop BW can be chosen very aggressively to reject the noise, thus achieving a low jitter, high performance PLL. Furthermore, since this PLL can reliably operate over a wide operating range, it is a one-design-fits-all general purpose PLL.

摘要翻译： 宽带，宽工作范围，通用数字锁相环（PLL）在数字域内运行，除了相关的时间数字转换器（T2D）和数字控制振荡器（DCO）外。 通过快速校准T2D和DCO，无论输入时钟频率，电源电压，处理和温度如何，通过使用校准的相位频率检测（PFD）和DCO信息来对控制回路校正进行归一化来实现恒定的PLL环路BW 变化。 PLL环路BW与操作条件和半导体器件变化完全解耦。 这意味着可以非常积极地选择PLL环路BW来抑制噪声，从而实现低抖动，高性能的PLL。 此外，由于该PLL可以在宽的工作范围内可靠地工作，所以它是一个单一设计的通用PLL。