公开(公告)号：US20240049450A1

公开(公告)日：2024-02-08

申请号：US18381119

申请日：2023-10-17

Applicant: Intel Corporation

Inventor： Travis W. LAJOIE ,  Abhishek A. SHARMA ,  Van H. LE ,  Chieh-Jen KU ,  Pei-Hua WANG ,  Jack T. KAVALIEROS ,  Bernhard SELL ,  Tahir GHANI ,  Gregory GEORGE ,  Akash GARG ,  Allen B. GARDINER ,  Shem OGADHOH ,  Juan G. ALZATE VINASCO ,  Umut ARSLAN ,  Fatih HAMZAOGLU ,  Nikhil MEHTA ,  Jared STOEGER ,  Yu-Wen HUANG ,  Shu ZHOU

IPC: H10B12/00 ,  H01L27/12

CPC classification number: H10B12/315 ,  H01L27/1218 ,  H01L27/1222 ,  H01L27/1225 ,  H01L28/82 ,  H01L27/1248 ,  H01L27/1255 ,  H01L28/55 ,  H01L28/65 ,  H01L27/124 ,  H10B12/312 ,  H10B12/0335

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.

公开(公告)号：US20230387315A1

公开(公告)日：2023-11-30

申请号：US18227233

申请日：2023-07-27

Applicant: Intel Corporation

Inventor： Abhishek A. SHARMA ,  Van H. LE ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Gilbert DEWEY

IPC: H01L29/786 ,  H01L29/423

CPC classification number: H01L29/78648 ,  H01L29/42384 ,  H01L29/78603 ,  H01L29/78672 ,  H01L29/7869 ,  H01L2029/42388

Abstract: Thin film transistors having double gates are described. In an example, an integrated circuit structure includes an insulator layer above a substrate. A first gate stack is on the insulator layer. A polycrystalline channel material layer is on the first gate stack. A second gate stack is on a first portion of the polycrystalline channel material layer, the second gate stack having a first side opposite a second side. A first conductive contact is adjacent the first side of the second gate stack, the first conductive contact on a second portion of the channel material layer. A second conductive contact is adjacent the second side of the second gate stack, the second conductive contact on a third portion of the channel material layer.

公开(公告)号：US20230317822A1

公开(公告)日：2023-10-05

申请号：US17711434

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Stephen M. CEA ,  Borna OBRADOVIC ,  Rishabh MEHANDRU ,  Jack T. KAVALIEROS

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/66553 ,  H01L29/66545 ,  H01L29/0673 ,  H01L29/0847

Abstract: Embodiments described herein may be related to transistor structures where dimpled spacers, which may also be referred to as inner spacers or offset spacers, may be formed around gates within an epitaxial structure such that the epitaxial material adjacent to the dimpled spacer is uniform and/or defect free. In embodiments, forming the dimpled spacers occurs after epitaxial growth. Other embodiments may be described and/or claimed.

公开(公告)号：US20230100505A1

公开(公告)日：2023-03-30

申请号：US17485238

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Ashish Verma PENUMATCHA ,  Sarah ATANASOV ,  Seung Hoon SUNG ,  Rahul RAMAMURTHY ,  I-Cheng TUNG ,  Uygar E. AVCI ,  Matthew V. METZ ,  Jack T. KAVALIEROS ,  Chia-Ching LIN ,  Kaan OGUZ

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/66

Abstract: Embodiments disclosed herein include transistor devices and methods of forming such devices. In an embodiment, a transistor device comprises a first channel, wherein the first channel comprises a semiconductor material and a second channel above the first channel, wherein the second channel comprises the semiconductor material. In an embodiment, a first spacer is between the first channel and the second channel, and a second spacer is between the first channel and the second channel. In an embodiment, a first gate dielectric is over a surface of the first channel that faces the second channel, and a second gate dielectric is over a surface of the second channel that faces the first channel. In an embodiment, the first gate dielectric is physically separated from the second gate dielectric.

公开(公告)号：US20220406895A1

公开(公告)日：2022-12-22

申请号：US17869622

申请日：2022-07-20

Applicant: Intel Corporation

Inventor： Siddharth CHOUKSEY ,  Glenn GLASS ,  Anand MURTHY ,  Harold KENNEL ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Ashish AGRAWAL ,  Seung Hoon SUNG

IPC: H01L29/165 ,  H01L21/8234 ,  H01L29/06 ,  H01L27/088

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.

公开(公告)号：US20220199773A1

公开(公告)日：2022-06-23

申请号：US17129860

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Jack T. KAVALIEROS ,  Siddharth CHOUKSEY ,  Ashish AGRAWAL

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: Integrated circuit structures having condensed source or drain structures with high germanium content are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. Each of the first and second epitaxial source or drain structures includes silicon and germanium, with an atomic concentration of germanium greater at a core of the epitaxial source or drain structure than at a periphery of the epitaxial source or drain structure.

公开(公告)号：US20220102521A1

公开(公告)日：2022-03-31

申请号：US17033471

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Nazila HARATIPOUR ,  Siddharth CHOUKSEY ,  Jack T. KAVALIEROS ,  Jitendra Kumar JHA ,  Matthew V. METZ ,  Mengcheng LU ,  Anand S. MURTHY ,  Koustav GANGULY ,  Ryan KEECH ,  Glenn A. GLASS ,  Arnab SEN GUPTA

IPC: H01L29/45 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/08 ,  H01L29/78 ,  H01L21/285 ,  H01L29/66

Abstract: Low resistance approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is directly on the first or second semiconductor source or drain structure, the source or drain contact including a barrier layer and an inner conductive structure.

公开(公告)号：US20220028972A1

公开(公告)日：2022-01-27

申请号：US17493695

申请日：2021-10-04

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Cheng-Ying HUANG ,  Matthew V. METZ ,  Nicholas G. MINUTILLO ,  Sean T. MA ,  Anand S. MURTHY ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Gilbert DEWEY

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/205 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).

公开(公告)号：US20210366821A1

公开(公告)日：2021-11-25

申请号：US17398933

申请日：2021-08-10

Applicant: Intel Corporation

Inventor： Travis LAJOIE ,  Abhishek SHARMA ,  Juan ALZATE-VINASCO ,  Chieh-Jen KU ,  Shem OGADHOH ,  Allen GARDINER ,  Blake LIN ,  Yih WANG ,  Pei-Hua WANG ,  Jack T. KAVALIEROS ,  Bernhard SELL ,  Tahir GHANI

IPC: H01L23/522 ,  H01L49/02 ,  H01L27/108 ,  H01L23/532

Abstract: An interconnect structure is disclosed. The interconnect structure includes a first metal interconnect in a bottom dielectric layer, a via that extends through a top dielectric layer, a metal plate, an intermediate dielectric layer, and an etch stop layer, and a metal in the via to extend through the top dielectric layer, the metal plate, the intermediate dielectric layer and the etch stop layer to the top surface of the first metal interconnect. The metal plate is coupled to an MIM capacitor that is parallel to the via. The second metal interconnect is on top of the metal in the via.

公开(公告)号：US20210125992A1

公开(公告)日：2021-04-29

申请号：US16645362

申请日：2017-12-22

Applicant: Intel Corporation

Inventor： Travis LAJOIE ,  Tahir GHANI ,  Jack T. KAVALIEROS ,  Shem O. OGADHOH ,  Yih WANG ,  Bernhard SELL ,  Allen GARDINER ,  Blake LIN ,  Juan G. ALZATE VINASCO ,  Pei-Hua WANG ,  Chieh-Jen KU ,  Abhishek A. SHARMA

IPC: H01L27/108 ,  H01L27/12

Abstract: Embodiments herein describe techniques for a semiconductor device having an interconnect structure above a substrate. The interconnect structure may include an inter-level dielectric (ILD) layer and a separation layer above the ILD layer. A first conductor and a second conductor may be within the ILD layer. The first conductor may have a first physical configuration, and the second conductor may have a second physical configuration different from the first physical configuration. Other embodiments may be described and/or claimed.