公开(公告)号：US5767583A

公开(公告)日：1998-06-16

申请号：US906005

申请日：1997-08-04

Applicant: Jae Jin Lee ,  Jung Pil Kim

Inventor： Jae Jin Lee ,  Jung Pil Kim

IPC: G11C5/00 ,  G11C5/14 ,  H01L23/50 ,  H01L23/48

CPC classification number: H01L23/50 ,  H01L24/06 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/30105

Abstract: A semiconductor device including outer pins including power pins adapted to supply a source voltage or a ground voltage, data pins adapted to input and output data and classified into a plurality of data pin groups having the same number of data pins, and output voltage pins adapted to supply output voltages of data pins of the data pin groups respectively associated therewith, wherein each of the output voltage pins is arranged between a pair of sub-groups constituting one of the data pin groups associated therewith, thereby capable of minimizing a resistance generated between each output voltage pin and each of data pins driven by the output voltage pin and achieving an improvement in data output characteristic.

Abstract translation: 一种半导体器件，包括外部引脚，其包括适于提供源极电压或接地电压的电源引脚，适于输入和输出数据并分类为具有相同数量引脚数量的多个数据引脚组的数据引脚和适配的输出电压引脚 以提供与其分别相关联的数据引脚组的数据引脚的输出电压，其中每个输出电压引脚布置在构成与其相关联的数据引脚组之一的一对子组之间，从而能够最小化在 每个输出电压引脚和每个数据引脚由输出电压引脚驱动，并实现数据输出特性的提高。

公开(公告)号：US5696720A

公开(公告)日：1997-12-09

申请号：US777199

申请日：1996-12-27

Applicant: Jae Jin Lee

Inventor： Jae Jin Lee

IPC: G11C11/34 ,  G11C7/10 ,  G11C7/00

CPC classification number: G11C7/1078

Abstract: A semiconductor memory device comprising a plurality of memory cells for storing data therein, a data input buffer circuit for buffering an input data signal, a data register circuit for storing the input data signal therein, a switching element for transferring the input data signal to the data register circuit, a register set control logic unit for controlling the switching element, a register set decoding circuit for decoding an output signal from the register set control logic unit and a first address signal, a write data drive circuit for transferring an output data signal from the data input buffer circuit or the data register circuit to a selected one of the memory cells, a first data transfer element for transferring the output data signal from the data input buffer circuit to the write data drive circuit, a second data transfer element for transferring the output data signal from the data register circuit to the write data drive circuit, a data transfer control circuit for generating first and second control signals to control the first and second data transfer element, respectively, and a data register output control circuit for decoding the second control signal from the data transfer control circuit and a second address signal.

Abstract translation: 一种半导体存储器件，包括用于存储数据的多个存储单元，用于缓冲输入数据信号的数据输入缓冲电路，用于存储输入数据信号的数据寄存器电路，用于将输入数据信号传送到 数据寄存器电路，用于控制开关元件的寄存器组控制逻辑单元，用于对来自寄存器组控制逻辑单元的输出信号进行解码的寄存器组解码电路和第一地址信号，用于传送输出数据信号的写数据驱动电路 从所述数据输入缓冲器电路或所述数据寄存器电路到所选存储单元中的一个，用于将所述输出数据信号从所述数据输入缓冲器电路传送到所述写数据驱动电路的第一数据传送元件，用于 将输出数据信号从数据寄存器电路传送到写数据驱动电路，用于发生数据传输控制电路 分别控制第一和第二数据传送元件的第一和第二控制信号，以及用于从数据传送控制电路解码第二控制信号的数据寄存器输出控制电路和第二地址信号。

公开(公告)号：US09685821B2

公开(公告)日：2017-06-20

申请号：US14435532

申请日：2013-10-08

Applicant: Jae Jin Lee

Inventor： Jae Jin Lee ,  Kyo Beum Lee

IPC: H02J9/00 ,  H02J9/06 ,  H02J7/00

CPC classification number: H02J9/061 ,  H02J7/0068

Abstract: Provided is an uninterruptible direct current (DC) power supply system, which includes a first connection unit electrically connected to a DC power conversion system which converts prevailing AC power into the DC power, a second connection unit which is electrically connected to the load and supplies the DC power to the load, an auxiliary power supply charged by the DC power, and an uninterruptible control unit which supplies the DC power supplied from the DC power conversion system normally connected to the first connection unit to the load through the second connection unit, charges the auxiliary power supply, and controls power to be continuously supplied to the load while perfectly cutting off electrical connection between the DC power conversion system and the auxiliary power supply when the DC power conversion system is disconnected from the first connection unit, is damaged, or short-circuits.

公开(公告)号：US08779797B2

公开(公告)日：2014-07-15

申请号：US13544548

申请日：2012-07-09

Applicant: Sang Jin Byeon ,  Jae Jin Lee

Inventor： Sang Jin Byeon ,  Jae Jin Lee

IPC: H03K19/173

CPC classification number: H03K19/173

Abstract: A semiconductor apparatus has a plurality of chips stacked therein, and generation timing of read control signals for controlling read operations of the plurality of stacked chips is controlled such that times after a read command is applied to when data are outputted from respective chips are made to substantially correspond to one another.

Abstract translation: 半导体装置具有堆叠的多个芯片，并且控制用于控制多个堆叠芯片的读取操作的读取控制信号的生成定时，使得在将读取命令应用于从各个芯片输出数据之后的时间被制成 基本相对应。

公开(公告)号：US08692282B2

公开(公告)日：2014-04-08

申请号：US13340867

申请日：2011-12-30

Applicant: Byoung Sung Kim ,  Sang Eun Lim ,  Jae Jin Lee ,  Yeoun Chul Son

Inventor： Byoung Sung Kim ,  Sang Eun Lim ,  Jae Jin Lee ,  Yeoun Chul Son

IPC: H01L33/00

CPC classification number: H01L33/486 ,  H01L33/62 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49107 ,  H05K1/0268 ,  H05K1/181 ,  H05K3/3426 ,  H05K2201/09427 ,  H05K2201/10106 ,  Y02P70/613 ,  H01L2924/00014

Abstract: Exemplary embodiments of the present invention provide a light emitting diode package including a light emitting diode chip, a lead frame having a chip area on which the light emitting diode chip is arranged, and a package body supporting the lead frame. The lead frame includes a first terminal group arranged at a first side of the chip area and a second terminal group arranged at a second side of the chip area. The first terminal group and the second terminal group each include a first terminal and a second terminal, and in at least one of the first terminal group and the second terminal group, the first terminal is connected to the chip area and the second terminal is separated from the chip area. The first terminal has a first width, the second terminal has a second width, and the first width is different than the second width.

Abstract translation: 本发明的示例性实施例提供一种包括发光二极管芯片的发光二极管封装，其上布置有发光二极管芯片的芯片区域的引线框架和支撑引线框架的封装体。 引线框架包括布置在芯片区域的第一侧的第一端子组和布置在芯片区域的第二侧的第二端子组。 第一端子组和第二端子组各自包括第一端子和第二端子，并且在第一端子组和第二端子组中的至少一个中，第一端子连接到芯片区域，并且第二端子被分离 从芯片区域。 第一端子具有第一宽度，第二端子具有第二宽度，并且第一宽度不同于第二宽度。

公开(公告)号：US08520725B2

公开(公告)日：2013-08-27

申请号：US13407546

申请日：2012-02-28

Applicant: Chun Seok Jeong ,  Jae Jin Lee ,  Chang Sik Yoo ,  Jang Woo Lee ,  Seok Joon Kang

Inventor： Chun Seok Jeong ,  Jae Jin Lee ,  Chang Sik Yoo ,  Jang Woo Lee ,  Seok Joon Kang

IPC: H03H7/30

CPC classification number: H04L25/03038

Abstract: A data equalizing circuit includes an equalizer configured to control a gain of data according to a value of a control code and output a controller gain; and a detection unit configured to divide n cycles of the data into N periods, count data transition frequencies for n/N periods while changing the value of the control code, calculate dispersion values of data transition frequencies for 1/N periods of the data from the data transition frequencies for the n/N periods, and finally output the value of the control code corresponding to a largest dispersion value, wherein n is equal to or greater than 2 and is set such that boundaries of the respective n/N periods of the data have different positions in the 1 UI data.

Abstract translation: 数据均衡电路包括均衡器，其被配置为根据控制码的值控制数据的增益并输出控制器增益; 以及检测单元，被配置为将数据的n个周期分成N个周期，在改变控制码的值的同时，计算n / N个周期的数据转换频率，计算数据的1 / N个周期的数据转换频率的色散值， n / N周期的数据转换频率，最后输出对应于最大色散值的控制码的值，其中n等于或大于2，并且被设置为使得各个n / N周期的边界 数据在1 UI数据中具有不同的位置。

公开(公告)号：US20110187408A1

公开(公告)日：2011-08-04

申请号：US12836546

申请日：2010-07-14

Applicant: Sang Jin Byeon ,  Jae Jin Lee

Inventor： Sang Jin Byeon ,  Jae Jin Lee

IPC: H03K19/173

CPC classification number: H03K19/173

Abstract: A semiconductor apparatus has a plurality of chips stacked therein, and generation timing of read control signals for controlling read operations of the plurality of stacked chips is controlled such that times after a read command is applied to when data are outputted from respective chips are made to substantially correspond to one another.

Abstract translation: 半导体装置具有堆叠的多个芯片，并且控制用于控制多个堆叠芯片的读取操作的读取控制信号的生成定时，使得在将读取命令应用于从各个芯片输出数据之后的时间被制成 基本相对应。

公开(公告)号：US20110085601A1

公开(公告)日：2011-04-14

申请号：US12836979

申请日：2010-07-15

Applicant: Jae Jin Lee ,  Jun Young Lee ,  Moo Kyoung Chung ,  Seong Mo Park ,  Nak Woong Eum

Inventor： Jae Jin Lee ,  Jun Young Lee ,  Moo Kyoung Chung ,  Seong Mo Park ,  Nak Woong Eum

IPC: H04N7/26

CPC classification number: H04N19/436 ,  H04N19/44

Abstract: Disclosed are a multiprocessor-based video decoding apparatus and method. The multiprocessor-based video decoding apparatus includes: a stream parser dividing an input stream by row and parsing a skip counter and a quantization parameter of the input stream; and a plurality of processors acquiring the plurality of divided streams, the skip counter, and the quantization parameter generated by the stream parser, acquiring decoded information of an upper processor among neighboring processors by row, and parallel-decoding the plurality of divided streams by row. Decoding of an input stream can be parallel-processed by row.

Abstract translation: 公开了一种基于多处理器的视频解码装置和方法。 基于多处理器的视频解码装置包括：流分析器，其逐行分割输入流，解析跳过计数器和输入流的量化参数; 以及多个处理器，获取多个划分的流，跳过计数器和由流解析器生成的量化参数，通过行获取相邻处理器之间的上位处理器的解码信息，并且按行并行解码多个划分的流 。 输入流的解码可以由行并行处理。

公开(公告)号：US20110008824A1

公开(公告)日：2011-01-13

申请号：US12520253

申请日：2008-08-28

Applicant: Jae Jin Lee ,  Chung Hwan Kim ,  Min Gun Kim

Inventor： Jae Jin Lee ,  Chung Hwan Kim ,  Min Gun Kim

IPC: C12Q1/04 ,  C12M1/42

CPC classification number: G01N33/56911 ,  C12M41/36

Abstract: A bacteria measurement device and method are provided, which separate bacteria from a target object and attach the bacteria to an antibody with fluorescein isothiocyanate applied thereto, generate light using a light emitting unit, and excite the fluorescein isothiocyanate, and in which the excited fluorescein isothiocyanate secondarily emits light, and a light receiving unit receives a light output signal generated through the secondary emission, converts the light output signal into an electrical signal, and converts an analog signal which is the electrical signal into a digital signal, thus measuring the amount and type of bacteria.

Abstract translation: 提供了一种细菌测量装置和方法，其将细菌与目标物体分离并将细菌附着于施用有异硫氰酸荧光素的抗体，使用发光单元产生光，并激发异硫氰酸荧光素，并且其中激发的异硫氰酸荧光素 二次发光，并且光接收单元接收通过二次发射产生的光输出信号，将光输出信号转换为电信号，并将作为电信号的模拟信号转换为数字信号，从而测量数量和 细菌类型

公开(公告)号：US07728369B2

公开(公告)日：2010-06-01

申请号：US11717145

申请日：2007-03-13

Applicant: Hee Bok Kang ,  Jin Hong Ahn ,  Jae Jin Lee

Inventor： Hee Bok Kang ,  Jin Hong Ahn ,  Jae Jin Lee

IPC: H01L29/94

CPC classification number: H01L27/11502 ,  G11C11/22 ,  H01L21/84 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7841

Abstract: A nonvolatile ferroelectric memory device is provided so as to control read/write operations of a nonvolatile memory cell using a channel resistance of the memory cell which is differentiated by polarity states of a ferroelectric material. In the memory device, an insulating layer is formed on a bottom word line, and a floating channel layer comprising a N-type drain region, a P-type channel region and a N-type source region is formed on the insulating layer. Then, a ferroelectric layer is formed on the floating channel layer, and a word line is formed on the ferroelectric layer. As a result, the resistance state induced to the channel region is controlled depending on the polarity of the ferroelectric layer, thereby regulating the read/write operations of the memory cell array.