公开(公告)号：US07772423B2

公开(公告)日：2010-08-10

申请号：US12257163

申请日：2008-10-23

申请人： Fuat E. Celik ,  Tae-Jin Kim ,  Alexis T. Bell

发明人： Fuat E. Celik ,  Tae-Jin Kim ,  Alexis T. Bell

IPC分类号： C07C67/36

CPC分类号： C07C67/37 ,  C07C69/708

摘要： A process for the production of lower alkyl alkoxyacetates, preferably methyl methoxyacetate, by reaction of a di-(lower alkoxy)methane, preferably dimethoxymethane, with the acid form of a medium-pore or large-pore zeolite catalyst, preferably the acid form of faujasite, ZSM-5, mordenite, or beta, in the gas phase at atmospheric or near-atmospheric pressures.

摘要翻译： 通过二 - （低级烷氧基）甲烷，优选二甲氧基甲烷与酸性形式的中孔或大孔沸石催化剂的反应制备低级烷基烷氧基乙酸酯，优选甲氧基乙酸甲酯的方法，优选酸 八面沸石，ZSM-5，丝光沸石或β，在大气压或接近大气压下的气相中。

公开(公告)号：US20100095141A1

公开(公告)日：2010-04-15

申请号：US12587826

申请日：2009-10-14

申请人： Tae-Jin Kim ,  Jung-Hun Park ,  Hyuk-Chan Park ,  Ho-Seung Lee ,  Kang-Min Lee

发明人： Tae-Jin Kim ,  Jung-Hun Park ,  Hyuk-Chan Park ,  Ho-Seung Lee ,  Kang-Min Lee

IPC分类号： G06F1/32 ,  G06F1/26 ,  G06F13/24

CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A portable communication apparatus is configured to perform a method for a power control of a Central Processing Unit (CPU) in a portable communication apparatus. The portable communication apparatus for a power control of the CPU includes a CPU for reporting an operation status of the CPU. The CPU is configured to change a power control level according to a control of an overhead determiner by using a pin and the overhead determiner for determining an overhead of the CPU by using the pin and for controlling the power control level of the CPU according to the overhead of the CPU.

摘要翻译： 便携式通信装置被配置为执行便携式通信装置中的中央处理单元（CPU）的功率控制方法。 用于CPU的功率控制的便携式通信装置包括用于报告CPU的操作状态的CPU。 CPU被配置为通过使用引脚和用于通过使用引脚来确定CPU的开销的开销确定器来根据开销确定器的控制来改变功率控制级别，并且用于根据所述引脚控制CPU的功率控制级别 CPU的开销。

公开(公告)号：US20090184743A1

公开(公告)日：2009-07-23

申请号：US12318306

申请日：2008-12-24

申请人： Tae-Jin Kim ,  Jang Jin Nam

发明人： Tae-Jin Kim ,  Jang Jin Nam

IPC分类号： H03L7/00 ,  H03H11/16

CPC分类号： H03K5/135 ,  G06F1/10 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/0814 ,  H04L7/0008 ,  H04L7/0337

摘要： A deskew system includes a first voltage control delay receiving a data signal and generating N-numbered delayed data signals obtained by delaying a phase of the data signal in units of 90/N, where N is a natural number that is not less than 1. In response to a phase control signal, a second voltage control delay receives a clock and generates N-numbered delayed clocks by delaying a phase of the clock in units of 90/N. A skew compensation control unit generates a plurality of skew control signals to compensate for skew between the data signal and the clock based on the data signal, the N-numbered delayed data signals, the clock, and the N-numbered delayed clocks.

摘要翻译： 一种偏移校正系统包括接收数据信号的第一电压控制延迟，并产生通过以90 / N为单位延迟数据信号的相位而获得的N编延迟数据信号，其中N是不小于1的自然数。 响应于相位控制信号，第二电压控制延迟通过以90 / N为单位延迟时钟的相位来接收时钟并产生N编延迟的时钟。 偏斜补偿控制单元基于数据信号，N编延迟数据信号，时钟和N编延迟时钟产生多个偏斜控制信号，以补偿数据信号和时钟之间的偏差。

公开(公告)号：US5631871A

公开(公告)日：1997-05-20

申请号：US578151

申请日：1995-12-29

申请人： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

发明人： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

IPC分类号： G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409 ,  B01F7/00 ,  B01F13/00

CPC分类号： G11C7/1018 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C2207/2281

摘要： A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

摘要翻译： 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于 灭活信号在预充电循环中工作。