Reconfigurable signal processor architecture using multiple complex multiply-accumulate units
    71.
    发明申请
    Reconfigurable signal processor architecture using multiple complex multiply-accumulate units 审中-公开
    可重构的信号处理器架构,使用多个复数乘法单元

    公开(公告)号:US20070106720A1

    公开(公告)日:2007-05-10

    申请号:US11584175

    申请日:2006-10-20

    IPC分类号: G06F7/38

    CPC分类号: G06F7/5443 H04B1/0003

    摘要: A reconfigurable digital signal processor (DSP) comprises: a reconfigurable data path comprising a plurality of reconfigurable multiply-accumulate (MAC) units; and a programmable finite state machine for controlling the plurality of reconfigurable MAC units. The programmable finite state machine executes a first plurality of context-related instructions that cause selected ones of the plurality of reconfigurable MAC units to perform at least one of a defined set of functions consisting essentially of: i) Fourier transform functions; and ii) filter functions. The Fourier transform functions comprise a Fast Fourier Transform (FFT) function and an Inverse Fast Fourier Transform (FFT) function and the filter functions comprise a finite impulse response (FIR) filter function and an infinite impulse response (IIR) filter function.

    摘要翻译: 可重配置数字信号处理器(DSP)包括:可重构数据路径,其包括多个可重构的乘法累加(MAC)单元; 以及用于控制多个可重构MAC单元的可编程有限状态机。 所述可编程有限状态机执行第一多个上下文相关指令,所述第一多个上下文相关指令使得所述多个可重新配置的MAC单元中的所选择的指令执行至少一个定义的功能集合,所述功能集合主要包括:i)傅立叶变换函数; 和ii)过滤功能。 傅立叶变换函数包括快速傅立叶变换(FFT)函数和快速傅里叶逆变换(FFT)函数,滤波器函数包括有限脉冲响应(FIR)滤波函数和无限脉冲响应(IIR)滤波函数。

    Method and system for optimizing a software-defined radio system

    公开(公告)号:US20060230187A1

    公开(公告)日:2006-10-12

    申请号:US11173131

    申请日:2005-07-01

    IPC分类号: G06F15/16

    CPC分类号: G06F15/16

    摘要: A method for optimizing a software-defined radio system comprising a plurality of processors is provided. The method includes, for each of the plurality of processors, (i) providing an input burst comprising a first specified burst size, M, of input words to the processor for each of a plurality of configurations, each input word comprising an integer, and (ii) receiving from the processor an output burst comprising a second specified burst size, N, of output words generated by the processor based on the M input words for each of the configurations. An optimization factor is determined for each of the configurations based on the N output words generated by each processor for the configuration. An optimized configuration is identified from the plurality of configurations based on the optimization factor of each of the configurations.

    Context-based operation reconfigurable instruction set processor and method of operation
    79.
    发明申请
    Context-based operation reconfigurable instruction set processor and method of operation 有权
    基于上下文的操作可重构指令集处理器和操作方法

    公开(公告)号:US20060184774A1

    公开(公告)日:2006-08-17

    申请号:US11123313

    申请日:2005-05-06

    IPC分类号: G06F9/44

    摘要: A reconfigurable context-based operation instruction set processor for use in a processing system capable of executing a first instruction set. The reconfigurable context-based operation instruction set processor comprises: 1) a reconfigurable data path comprising a plurality of reconfigurable functional blocks; and 2) a programmable finite state machine capable of controlling the reconfigurable data path. The programmable finite state machine is capable of executing a first plurality of context-related instructions that are a first subset of the first instruction set.

    摘要翻译: 一种可重构基于上下文的操作指令集处理器,用于能够执行第一指令集的处理系统。 所述可重新配置的基于上下文的操作指令集处理器包括:1)包括多个可重新配置功能块的可重构数据路径; 和2)能够控制可重构数据路径的可编程有限状态机。 可编程有限状态机能够执行作为第一指令集的第一子集的第一多个上下文相关指令。