摘要:
A desktop charger for a portable wireless terminal, comprising: a charger housing; a slot for receiving and holding a stationary body of the terminal, the slot being recessed a determined depth from the front side toward the rear side of the charger housing; and an opening for providing a rotation space for a rotatable body coupled to an end of the stationary body rotatably, the opening extending from a side of the slot in the transverse direction and penetrating the charger housing from its front side to its rear side. The lower body of the terminal can rotate even when the terminal is mounted on the desktop charger. Therefore, the user can perform video communication during charging by using the provided display device and camera lens unit. In addition, wireless communication modules installed at the desktop charger make the connection with an auxiliary device or data communication device easier.
摘要:
An automatic medicine packing system includes a packing envelope roll, a medicine supply unit that supplies a medicine dispensed from a tablet cassette according to prescription data, a sealing unit that heat seal a packing envelope, a database that stores prescription data, user data, and status data of the system, an wireless communication unit, an authentication unit that that authenticates the user data, a control unit, and a wireless terminal. The authentication unit includes multi-level user permission, and the authentication unit set particular level user permission according to the authentication result of the user. The multi-level user permission includes an administrator level, a packing operation user level and a monitoring operation user level. The wireless terminal includes a smart chip that contains user's authentication data.
摘要:
Disclosed herein are circuits in which a plurality of clock signals are generated by corresponding clock generators from one or more common clock references. The clock generators accept control values that specify the phases of the individual clocks. The actual phase of each clock signal potentially varies during operation, and the phases of the various clock signal are generally independent of each other. To detect or measure phase relationships, the disclosed circuits evaluate or compare the control values using arithmetic logic.
摘要:
An apparatus for monitoring a tire pressure using a radio frequency identification system wherein a pressure and a temperature of a tire is constantly monitored for a driver to predict a dangerous situation that may occur in a future and to take a prompt action on the predicted dangerous situation is disclosed. The apparatus comprises a tag for measuring a pressure and a temperature of a tire installed on each of wheels, a reader for providing a power to the tag and for receiving and processing a pressure and temperature information provided by the reader, and a display device for receiving the processed pressure and temperature information and displaying the received pressure and temperature information.
摘要:
A composite polyamide reverse osmosis membrane and method of producing same. In a preferred embodiment, the membrane is made by coating a porous polysulfone support with an aqueous solution containing 2 wt % m-phenylenediamine (MPD), and 0.1 wt % di(ethylene glycol) hexyl methyl ether. Next, the excess solution is removed, and the coated support is dipped in 0.1 wt % organic solvent solution of trimesoyl chloride (TMC) in a mixture of alkanes having from 8 to 12 carbon atoms. After draining the TMC solution off, the resulting composite membrane is air dried and then rinsed in a basic aqueous solution. The resultant membrane exhibits a flux of 21.3 gfd and a salt rejection of 98.9% when used at 225 psi for an aqueous solution containing 2000 ppm of NaCl.
摘要:
Disclosed herein are a building management system (BMS) and an operating method thereof. A BMS controller of a LonWorks network integrally controls a multi-air conditioner system which uses a different communication scheme, without modification of the structure thereof. The building management system comprises a BMS controller (50) for centrally controlling subsystems (60 and 70) installed in the building and connected to a LonWorks network (N2), an air conditioner system (70) including a plurality of outdoor units (71) and a plurality of indoor units (72) connected to the outdoor units, and a Lon gateway (80) for converting data of an air conditioner system network (N1) into data of the LonWorks network (N2), and vice versa, to enable the BMS controller (50) to centrally control the air conditioner system (70). The building management system can incorporate a multi-air conditioner system which utilizes a different communication technology, without modification. The building management system also facilitates low-cost installation of an integrated control system in the building because each one of the indoor units constituting the multi-air conditioner system can be separately controlled without the need for a communication module to be connected to each indoor unit.
摘要:
Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used in the path of the, delayed output clock or the output clock.
摘要:
A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in dynamic memory bank count and page size mode. The integrated circuit memory device includes a first and second row of storage cells coupled to a row of sense amplifiers including a first and second plurality of sense amplifiers. During the first mode of operation, a first plurality of data is transferred from the first plurality of storage cells to the row of sense amplifiers. During the second mode of operation, a second plurality of data is transferred from the first row of storage cells to the first plurality of sense amplifiers and a third plurality of data is transferred from the second row of storage cells to the second plurality of sense amplifiers. The second and third plurality of data is accessible simultaneously from the memory device interface during the second mode of operation. In an embodiment, the second plurality of data is transferred from the first half of the first row and the third plurality of data is transferred from the second half of the second row.
摘要:
A circuit defining a second system clock in a system comprising a master connected to one or more slave devices via a channel, the channel communicating an externally generated first system clock towards the master. The circuit comprising a delay locked loop circuit configured to receive the first system clock and a second phase feedback signal as inputs and to generate a transmit clock signal. A 90 degrees block configured to receive the transmit system clock and to generate a 90 degrees phased shifted version of the transmit clock signal. An output driver circuit configured to receive the 90 degrees phased shifted version of the transmit clock signal and to generate the second system clock. A first phase detector configured to receive a receive system clock and the transmit system clock and to generate a first phase feedback signal. A delay element configured to receive the first system clock and the first phase feedback signal and to generate a delayed first system clock. A second phase detector configured to receive the delayed first system clock and the second system clock and to generate the second phase feedback signal.