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公开(公告)号:US10148581B2
公开(公告)日:2018-12-04
申请号:US15168118
申请日:2016-05-30
Applicant: Mellanox Technologies Ltd.
Inventor: Ariel Shahar , Hillel Chapman
IPC: H04L12/801 , H04L12/24 , H04L5/00
Abstract: A method for communication includes establishing, using an end-to-end reliable transport context, a channel for exchange of data packets over a network between a first network interface controller (NIC) of a first computing node on the network and a second NIC of a second computing node on the network. The first NIC accepts first and second work items for execution on behalf of different, first and second sender processes, respectively, that are running on the first computing node. The first and second work items are executed by transmitting over the network from the first NIC to the second NIC, using the end-to-end reliable transport context, first and second messages directed to different, first and second receiver process running on the second computing node, using the same end-to-end reliable transport context. The second message is sent before receiving from the second NIC any acknowledgment of the first message.
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公开(公告)号:US09996498B2
公开(公告)日:2018-06-12
申请号:US14847021
申请日:2015-09-08
Applicant: MELLANOX TECHNOLOGIES LTD.
Inventor: Ariel Shahar , Maria Lubeznov
IPC: G06F15/167 , G06F15/173 , H04L29/08 , H04L12/861 , H04L12/933
CPC classification number: G06F15/17331 , H04L49/15 , H04L49/9068 , H04L67/1097
Abstract: Communication apparatus includes a host interface for connection, via a host bus, to a host processor and a host memory, which is mapped to an address space of the host bus, and a network interface, configured to transmit and receive packets over a network. A local memory is configured to hold data in a memory space that is not mapped to the address space of the host bus. Packet processing circuitry, which is connected between the host interface and the network interface and is connected to the local memory, is configured to receive from the network interface a packet carrying a remote direct memory access (RDMA) request that is directed to an address in the local memory, and to service the RDMA request by accessing the data in the local memory.
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公开(公告)号:US20170346742A1
公开(公告)日:2017-11-30
申请号:US15168118
申请日:2016-05-30
Applicant: Mellanox Technologies Ltd.
Inventor: Ariel Shahar , Hillel Chapman
IPC: H04L12/801 , H04L12/24 , H04L5/00
CPC classification number: H04L47/18 , H04L5/0055 , H04L47/11
Abstract: A method for communication includes establishing, using an end-to-end reliable transport context, a channel for exchange of data packets over a network between a first network interface controller (NIC) of a first computing node on the network and a second NIC of a second computing node on the network. The first NIC accepts first and second work items for execution on behalf of different, first and second sender processes, respectively, that are running on the first computing node. The first and second work items are executed by transmitting over the network from the first NIC to the second NIC, using the end-to-end reliable transport context, first and second messages directed to different, first and second receiver process running on the second computing node, using the same end-to-end reliable transport context. The second message is sent before receiving from the second NIC any acknowledgment of the first message.
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公开(公告)号:US09742855B2
公开(公告)日:2017-08-22
申请号:US14834443
申请日:2015-08-25
Applicant: Mellanox Technologies Ltd.
Inventor: Shahaf Shuler , Noam Bloch , Ofer Hayut , Richard Graham , Ariel Shahar , Yossef Itigin
IPC: H04L29/08 , H04L29/06 , H04L12/861
CPC classification number: H04L67/26 , H04L49/9068 , H04L67/10 , H04L67/1093 , H04L67/1097 , H04L69/06
Abstract: A method for communication includes posting, by a software process, a set of buffers in a memory of a host processor and creating in the memory a list of labels associated respectively with the buffers. The software process pushes a first part of the list to a network interface controller (NIC), while retaining a second part of the list in the memory under control of the software process. Upon receiving a message containing a label, sent over a network, the NIC compares the label to the labels in the first part of the list and, upon finding a match to the label, writes data conveyed by the message to a buffer in the memory. Upon a failure to find the match in the first part of the list, the NIC passes the message from the NIC to the software process for handling using the second part of the list.
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公开(公告)号:US20160294926A1
公开(公告)日:2016-10-06
申请号:US15077945
申请日:2016-03-23
Applicant: Mellanox Technologies Ltd.
Inventor: Itay Zur , Noam Bloch , Ariel Shahar , Dotan Finkelstein
Abstract: A method for communication includes receiving multiple work requests from a process running on a computer to transmit respective messages over a network. A single work item corresponding to the multiple work requests is submitted to a network interface controller (NIC) connected to the computer. In response to the single work item, multiple data packets carrying the respective messages are transmitted from the NIC to the network.
Abstract translation: 一种用于通信的方法包括从计算机上运行的进程接收多个工作请求以通过网络发送相应的消息。 与多个工作请求相对应的单个工作项目被提交给连接到计算机的网络接口控制器(NIC)。 响应于单个工作项,携带相应消息的多个数据分组从NIC传送到网络。
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公开(公告)号:US20160248671A1
公开(公告)日:2016-08-25
申请号:US15145848
申请日:2016-05-04
Applicant: MELLANOX TECHNOLOGIES LTD.
Inventor: Nir Haim Arad , Noam Bloch , Ariel Shahar , Hillel Chapman , Amir Wated
IPC: H04L12/741 , H04L12/931
CPC classification number: H04L45/74 , H04L45/38 , H04L45/745 , H04L47/10 , H04L49/351 , H04L49/355 , H04L49/358 , H04L49/70
Abstract: A method for steering packets includes receiving a packet and determining parameters to be used in steering the packet to a specific destination, in one or more initial steering stages, based on one or more packet specific attributes. The method further includes determining an identity of the specific destination of the packet in one or more subsequent steering stages, governed by the parameters determined in the one or more initial stages and one or more packet specific attributes, and forwarding the packet to the determined specific destination.
Abstract translation: 一种用于转向分组的方法包括基于一个或多个分组特定属性,在一个或多个初始转向阶段中接收分组并确定要用于将分组指向特定目的地的参数。 该方法还包括确定一个或多个后续转向级中的分组的特定目的地的身份,由在一个或多个初始阶段中确定的参数和一个或多个分组特定属性来管理,以及将分组转发到所确定的特定 目的地。
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公开(公告)号:US12177325B2
公开(公告)日:2024-12-24
申请号:US18523991
申请日:2023-11-30
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Dotan David Levi , Ariel Shahar , Shahaf Shuler , Ariel Almog , Eitan Hirshberg , Natan Manevich
IPC: H04L7/00
Abstract: A communication system includes at least one send queue, containing send queue entries pointing to packets to be transmitted over a network by packet sending circuitry. A clock work queue contains clock queue entries to synchronize sending times of the packets pointed to by the send queue entries. At least one arming queue contains arming queue entries to arm the clock work queue at selected time intervals.
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公开(公告)号:US20240193106A1
公开(公告)日:2024-06-13
申请号:US18444804
申请日:2024-02-19
Applicant: Mellanox Technologies, Ltd.
Inventor: Idan Burstein , Dotan David Levi , Ariel Shahar , Lior Narkis , Igor Voks , Noam Bloch , Shay Aisman
IPC: G06F13/16 , G06F9/455 , G06F9/46 , G06F12/1045 , G06F13/38 , G06F13/42 , G06F15/173
CPC classification number: G06F13/1668 , G06F9/45558 , G06F9/466 , G06F12/1054 , G06F12/1063 , G06F13/387 , G06F13/4221 , G06F15/17331 , G06F2009/45579
Abstract: A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and first and second system components. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to cause the peripheral device to access the second address space that is associated with the second system component.
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79.
公开(公告)号:US11966355B2
公开(公告)日:2024-04-23
申请号:US16224834
申请日:2018-12-19
Applicant: Mellanox Technologies, Ltd.
Inventor: Ariel Shahar , Roee Moyal , Ali Ayoub , Michael Kagan
IPC: G06F15/173 , G06F13/28 , G06F15/167 , H04L9/06 , H04L9/32
CPC classification number: G06F15/17331 , G06F13/28 , G06F15/167 , G06F15/1735 , H04L9/0631 , H04L9/0643 , H04L9/3247
Abstract: A network adapter includes a network interface that communicates packets over a network, a host interface connected locally to a host processor and to a host memory, and processing circuitry, coupled between the network interface and the host interface, and is configured to receive in a common queue, via the host interface, (i) a processing work item specifying a source buffer in the host memory, a data processing operation, and a first address in the host memory, and (ii) an RDMA write work item specifying the first address, and a second address in a remote memory. In response to the processing work item, the processing circuitry reads data from the source buffer, applies the data processing operation, and stores the processed data in the first address. In response to the RDMA write work item the processing circuitry transmits the processed data, over the network, for storage in the second address.
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公开(公告)号:US11940933B2
公开(公告)日:2024-03-26
申请号:US17189303
申请日:2021-03-02
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Idan Burstein , Dotan David Levi , Ariel Shahar , Lior Narkis , Igor Voks , Noam Bloch , Shay Aisman
IPC: G06F13/16 , G06F9/455 , G06F9/46 , G06F12/1045 , G06F13/38 , G06F13/42 , G06F15/173
CPC classification number: G06F13/1668 , G06F9/45558 , G06F9/466 , G06F12/1054 , G06F12/1063 , G06F13/387 , G06F13/4221 , G06F15/17331 , G06F2009/45579
Abstract: A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and first and second system components. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to cause the peripheral device to access the second address space that is associated with the second system component.
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