I/O BUFFER OFFSET MITIGATION
    72.
    发明申请

    公开(公告)号:US20220359014A1

    公开(公告)日:2022-11-10

    申请号:US17873216

    申请日:2022-07-26

    Abstract: Memory including an array of memory cells might include an input buffer having calibration circuitry, a first input, a second input, and an output; and calibration logic having an input selectively connected to the output of the input buffer and comprising an output connected to the calibration circuitry, wherein the calibration logic is configured to cause the memory to determine whether the input buffer exhibits offset while a particular voltage level is applied to the first and second inputs of the input buffer, and, in response to determining that the selected input buffer exhibits offset, apply an adjustment to the calibration circuitry while the particular voltage level is applied to the first and second inputs until a logic level of the output of the selected input buffer transitions.

    Apparatus and methods for determining data states of memory cells

    公开(公告)号:US10854303B2

    公开(公告)日:2020-12-01

    申请号:US16908832

    申请日:2020-06-23

    Abstract: Methods of operating a memory, as well as memory configured to perform such methods, might include determining a plurality of read voltages for a read operation during a precharge phase of the read operation, determining a pass voltage for the read operation during the precharge phase of the read operation, applying the pass voltage to each unselected access line of a plurality of access lines, and, for each read voltage of the plurality of read voltages, applying that read voltage to a selected access line of the plurality of access lines and sensing a data state of a memory cell connected to the selected access line.

    Methods for determining data states of memory cells

    公开(公告)号:US10714196B2

    公开(公告)日:2020-07-14

    申请号:US16152897

    申请日:2018-10-05

    Abstract: Methods of operating a memory might include sensing a state of each data line of a plurality of data lines while increasing a voltage level applied to each access line of a plurality of access lines commonly connected to a plurality of strings of series-connected memory cells, determining a particular voltage level at which the state of each data line of a first subset of the plurality of data lines has changed, decreasing a voltage level applied to a particular access line of the plurality of access lines, and sensing a state of each data line of a second subset of the plurality of data lines while applying the particular voltage level to the particular access line. Methods of operating a memory might further include determining a pass voltage and plurality of read voltages for a read operation during a precharge phase of the read operation, applying the pass voltage to each unselected access line of a plurality of access lines, and, for each read voltage of the plurality of read voltages, applying that read voltage to a selected access line of the plurality of access lines and sensing a data state of a memory cell connected to the selected access line.

    METHODS FOR DETERMINING DATA STATES OF MEMORY CELLS

    公开(公告)号:US20200111534A1

    公开(公告)日:2020-04-09

    申请号:US16152897

    申请日:2018-10-05

    Abstract: Methods of operating a memory might include sensing a state of each data line of a plurality of data lines while increasing a voltage level applied to each access line of a plurality of access lines commonly connected to a plurality of strings of series-connected memory cells, determining a particular voltage level at which the state of each data line of a first subset of the plurality of data lines has changed, decreasing a voltage level applied to a particular access line of the plurality of access lines, and sensing a state of each data line of a second subset of the plurality of data lines while applying the particular voltage level to the particular access line. Methods of operating a memory might further include determining a pass voltage and plurality of read voltages for a read operation during a precharge phase of the read operation, applying the pass voltage to each unselected access line of a plurality of access lines, and, for each read voltage of the plurality of read voltages, applying that read voltage to a selected access line of the plurality of access lines and sensing a data state of a memory cell connected to the selected access line.

Patent Agency Ranking