公开(公告)号：US20240339149A1

公开(公告)日：2024-10-10

申请号：US18749412

申请日：2024-06-20

Applicant: Micron Technology, Inc.

Inventor： Joseph Michael McCrate ,  Robert John Gleixner ,  Hari Giduturi ,  Ramin Ghodsi

IPC: G11C11/408 ,  G11C11/4091 ,  G11C13/00

CPC classification number: G11C11/4087 ,  G11C11/4091 ,  G11C13/0002 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2211/4013

Abstract: The application relates to an architecture that allows for less precision of demarcation read voltages by combining two physical memory cells into a single logical bit. Reciprocal binary values may be written into the two memory cells that make up a memory pair. When activated using bias circuitry and address decoders the memory cell pair creates current paths having currents that may be compared to detect a differential signal. The application is also directed to writing and reading memory cell pairs.

公开(公告)号：US20220359014A1

公开(公告)日：2022-11-10

申请号：US17873216

申请日：2022-07-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Qiang Tang ,  Ramin Ghodsi

IPC: G11C16/10 ,  G11C16/04 ,  H03K19/00 ,  G11C16/26 ,  H03K19/0185 ,  G11C29/02 ,  G11C29/50 ,  G11C7/10

Abstract: Memory including an array of memory cells might include an input buffer having calibration circuitry, a first input, a second input, and an output; and calibration logic having an input selectively connected to the output of the input buffer and comprising an output connected to the calibration circuitry, wherein the calibration logic is configured to cause the memory to determine whether the input buffer exhibits offset while a particular voltage level is applied to the first and second inputs of the input buffer, and, in response to determining that the selected input buffer exhibits offset, apply an adjustment to the calibration circuitry while the particular voltage level is applied to the first and second inputs until a logic level of the output of the selected input buffer transitions.

公开(公告)号：US11145370B2

公开(公告)日：2021-10-12

申请号：US17065655

申请日：2020-10-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Feng Pan ,  Jaekwan Park ,  Ramin Ghodsi

IPC: G11C16/04 ,  G11C16/26 ,  G11C8/12 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C11/56

Abstract: Apparatuses and methods for segmented SGS lines are described. An example apparatus includes a plurality of memory subblocks, a plurality of first select gate control lines, each first select gate control line of the plurality of first select gate control lines configured to couple a memory subblock of the plurality of memory subblocks to a signal line, and a second select gate control line configured to couple the plurality of memory subblocks to a source line.

公开(公告)号：US10854303B2

公开(公告)日：2020-12-01

申请号：US16908832

申请日：2020-06-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Ramin Ghodsi

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C16/08 ,  G11C16/32

Abstract: Methods of operating a memory, as well as memory configured to perform such methods, might include determining a plurality of read voltages for a read operation during a precharge phase of the read operation, determining a pass voltage for the read operation during the precharge phase of the read operation, applying the pass voltage to each unselected access line of a plurality of access lines, and, for each read voltage of the plurality of read voltages, applying that read voltage to a selected access line of the plurality of access lines and sensing a data state of a memory cell connected to the selected access line.

公开(公告)号：US10803945B2

公开(公告)日：2020-10-13

申请号：US16457611

申请日：2019-06-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Feng Pan ,  Jaekwan Park ,  Ramin Ghodsi

IPC: G11C16/04 ,  G11C16/26 ,  G11C8/12 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C11/56

Abstract: Apparatuses and methods for segmented SGS lines are described. An example apparatus includes a plurality of memory subblocks, a plurality of first select gate control lines, each first select gate control line of the plurality of first select gate control lines configured to couple a memory subblock of the plurality of memory subblocks to a signal line, and a second select gate control line configured to couple the plurality of memory subblocks to a source line.

公开(公告)号：US10714196B2

公开(公告)日：2020-07-14

申请号：US16152897

申请日：2018-10-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Ramin Ghodsi

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C16/08 ,  G11C16/32

Abstract: Methods of operating a memory might include sensing a state of each data line of a plurality of data lines while increasing a voltage level applied to each access line of a plurality of access lines commonly connected to a plurality of strings of series-connected memory cells, determining a particular voltage level at which the state of each data line of a first subset of the plurality of data lines has changed, decreasing a voltage level applied to a particular access line of the plurality of access lines, and sensing a state of each data line of a second subset of the plurality of data lines while applying the particular voltage level to the particular access line. Methods of operating a memory might further include determining a pass voltage and plurality of read voltages for a read operation during a precharge phase of the read operation, applying the pass voltage to each unselected access line of a plurality of access lines, and, for each read voltage of the plurality of read voltages, applying that read voltage to a selected access line of the plurality of access lines and sensing a data state of a memory cell connected to the selected access line.

公开(公告)号：US20200111534A1

公开(公告)日：2020-04-09

申请号：US16152897

申请日：2018-10-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Ramin Ghodsi

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/08

Abstract: Methods of operating a memory might include sensing a state of each data line of a plurality of data lines while increasing a voltage level applied to each access line of a plurality of access lines commonly connected to a plurality of strings of series-connected memory cells, determining a particular voltage level at which the state of each data line of a first subset of the plurality of data lines has changed, decreasing a voltage level applied to a particular access line of the plurality of access lines, and sensing a state of each data line of a second subset of the plurality of data lines while applying the particular voltage level to the particular access line. Methods of operating a memory might further include determining a pass voltage and plurality of read voltages for a read operation during a precharge phase of the read operation, applying the pass voltage to each unselected access line of a plurality of access lines, and, for each read voltage of the plurality of read voltages, applying that read voltage to a selected access line of the plurality of access lines and sensing a data state of a memory cell connected to the selected access line.

公开(公告)号：US10325659B1

公开(公告)日：2019-06-18

申请号：US15864069

申请日：2018-01-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Qiang Tang ,  Ramin Ghodsi

IPC: H03K19/0185 ,  G11C16/10 ,  G11C16/04 ,  H03K19/00 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/26 ,  H03K19/0005 ,  H03K19/018528

Abstract: Methods of operating an integrated circuit device, and integrated circuit devices configured to perform methods, including applying a particular voltage level to a first input of an input/output (I/O) buffer and to a second input of the I/O buffer, determining whether the I/O buffer is deemed to exhibit offset, and applying an adjustment to the I/O buffer offset while applying the particular voltage level to the first input of the I/O buffer and to the second input of the I/O buffer if the I/O buffer is deemed to exhibit offset.

公开(公告)号：US20190074061A1

公开(公告)日：2019-03-07

申请号：US16123772

申请日：2018-09-06

Applicant: Micron Technology, Inc.

Inventor： Ramin Ghodsi

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/16 ,  G11C16/08 ,  G06F3/06 ,  G11C16/34 ,  G11C16/14

Abstract: Various embodiments comprise apparatuses such as those having a block of memory divided into sub-blocks that share a common data line. Each of the sub-blocks of the block of memory corresponds to a respective one of a number of segmented sources. Each of the segmented sources is electrically isolated from the other segmented sources of the block of memory. Additional apparatuses and methods of operation are described.

公开(公告)号：US20180308543A1

公开(公告)日：2018-10-25

申请号：US16023042

申请日：2018-06-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Qiang Tang ,  Xiaojiang Guo ,  Ramin Ghodsi

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/12 ,  G11C16/34 ,  G06F3/06

CPC classification number: G11C11/5628 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0688 ,  G06F12/0246 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3404 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5622

Abstract: Methods of operating a memory device applying a programming pulse having a plurality of different voltage levels to an access line coupled to a plurality of memory cells, enabling a particular memory cell of the plurality of memory cells for programming while the programming pulse has a particular voltage level of the plurality of different voltage levels, and, after enabling the particular memory cell for programming, inhibiting the particular memory cell from programming while the programming pulse has a second voltage level of the plurality of different voltage levels, different than the particular voltage level.