公开(公告)号：US6121094A

公开(公告)日：2000-09-19

申请号：US120246

申请日：1998-07-21

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L21/336

CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/28229 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： The present invention is directed to a new semiconductor device and a method for making same. The semiconductor device is comprised of a gate dielectric layer, a conductor layer, and a metal oxide layer positioned between the gate dielectric layer and the conductor layer. The method comprises forming a gate dielectric layer, a conductor layer, and a metal oxide layer between the gate dielectric layer and the conductor layer.

摘要翻译： 本发明涉及一种新的半导体器件及其制造方法。 该半导体器件由位于栅介电层和导体层之间的栅介电层，导体层和金属氧化物层构成。 该方法包括在栅极介电层和导体层之间形成栅极电介质层，导体层和金属氧化物层。

公开(公告)号：US6111292A

公开(公告)日：2000-08-29

申请号：US175800

申请日：1998-10-20

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L29/66583 ,  Y10S257/90

摘要： A method is provided for forming nitride sidewall spacers self-aligned between opposed sidewall surfaces of a gate conductor and a sacrificial dielectric sidewall. In one embodiment, a transistor is formed by first CVD depositing a sacrificial across a semiconductor substrate. An opening is etched through the dielectric to the underlying substrate. A gate oxide is thermally grown across the region of the substrate exposed by the first opening. A polysilicon gate conductor is then formed within the opening upon the gate oxide. Portions of the gate conductor and the gate oxide are removed to expose selective regions of the substrate. In this manner, a pair of opposed sidewall surfaces are defined for the polysilicon gate conductor which are laterally spaced from respective first and second dielectrics. A LDD implant is forwarded into those exposed selective regions of the semiconductor substrate. A dielectric, preferably nitride, is deposited by CVD across the exposed LDD areas of the semiconductor substrate, the sacrificial dielectric, and the gate conductor. The nitride is removed down to a plane level with the upper surface of the gate conductor. The sacrificial dielectric may then be removed from the semiconductor substrate. An ion implantation which is self-aligned to exposed lateral edges of the spacers may then be performed to form heavily doped source/drain regions laterally spaced from the channel.

摘要翻译： 提供一种用于形成在栅极导体和牺牲电介质侧壁的相对侧壁表面之间自对准的氮化物侧壁间隔件的方法。 在一个实施例中，通过首先在半导体衬底上沉积牺牲形成晶体管。 通过电介质将开口蚀刻到下面的衬底上。 栅极氧化物在由第一开口暴露的衬底的区域上热生长。 然后在栅极氧化物的开口内形成多晶硅栅极导体。 去除栅极导体和栅极氧化物的部分以露出衬底的选择性区域。 以这种方式，对于多晶硅栅极导体定义一对相对的侧壁表面，其与相应的第一和第二电介质横向间隔开。 LDD注入被转发到半导体衬底的暴露的选择区域中。 电介质，优选氮化物，通过CVD沉积在半导体衬底，牺牲电介质和栅极导体的暴露的LDD区域上。 将氮化物与栅极导体的上表面下降到平面水平。 然后可以从半导体衬底去除牺牲电介质。 然后可以执行与间隔物的暴露的横向边缘自对准的离子注入，以形成与沟道横向间隔开的重掺杂的源极/漏极区域。

公开(公告)号：US6100147A

公开(公告)日：2000-08-08

申请号：US61778

申请日：1998-04-16

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21/336 ,  H01L29/417

CPC分类号： H01L29/66575 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66545

摘要： A process for manufacturing a high performance transistor with self-aligned dopant profile. The process involves forming a source/drain mask pattern on a substrate. With a first implant material, unmasked portions of the substrate are doped to form source/drain regions of the substrate. The source-drain mask is removed and an oxidation layer is grown, where portions of the oxidation layer formed from doped regions of the substrate have heights that are greater than heights of portions of the oxidation layer formed from un-doped regions of the substrate, thereby forming a gate mask. The doped portions of the substrate are self-aligned with gate regions of the substrate. The gate regions are doped, and gate electrodes are formed. The gate mask is removed to expose source/drain regions of the substrate for further fabrication.

摘要翻译： 一种用于制造具有自对准掺杂剂分布的高性能晶体管的工艺。 该方法包括在衬底上形成源极/漏极掩模图案。 利用第一注入材料，衬底的未屏蔽部分被掺杂以形成衬底的源极/漏极区域。 去除源极 - 漏极掩模，并且生长氧化层，其中由衬底的掺杂区形成的部分氧化层的高度大于由衬底的未掺杂区域形成的部分氧化层的高度， 从而形成栅极掩模。 衬底的掺杂部分与衬底的栅极区域自对准。 栅区被掺杂，形成栅电极。 去除栅极掩模以暴露衬底的源极/漏极区域以进一步制造。

公开(公告)号：US6099387A

公开(公告)日：2000-08-08

申请号：US97607

申请日：1998-06-15

申请人： Mark C. Gilmer ,  Mark I. Gardner

发明人： Mark C. Gilmer ,  Mark I. Gardner

IPC分类号： B24B9/06 ,  B24B37/08 ,  B24B5/00 ,  B24B49/00

CPC分类号： B24B37/08 ,  B24B9/065

摘要： Apparatus and method for polishing one or both sides of a semiconductor wafer that has a central opening are provided. In one aspect, the apparatus includes a mandrel for holding the wafer and a motor coupled to the mandrel that is operable to rotate the mandrel. A first polisher assembly is provide that has a first polish pad for polishing the first side of the wafer and a second polish pad for polishing the second side of the wafer, and first means for moving the first and second polish pads into and out of engagement with the first and second sides of the wafer. According to the method, a semiconductor wafer is coupled to a rotatable mandrel and a polishing mixture is dispensed on one or both of the sides of the semiconductor wafer. A first polish pad is brought into contact with the first side of the semiconductor wafer and a second polish pad is brought into contact with the second side of the semiconductor wafer such that the first and second polish pads are positioned in opposition. The mandrel is rotated to spin the wafer.

摘要翻译： 提供了用于抛光具有中心开口的半导体晶片的一侧或两侧的装置和方法。 在一个方面，该装置包括用于保持晶片的心轴和联接到心轴的马达，其可操作以旋转心轴。 提供第一抛光器组件，其具有用于抛光晶片的第一侧的第一抛光垫和用于抛光晶片的第二侧的第二抛光垫，以及用于将第一和第二抛光垫移动和移出接合的第一装置 与晶片的第一和第二面。 根据该方法，将半导体晶片连接到可旋转的心轴，并且将抛光混合物分配在半导体晶片的一侧或两侧。 第一抛光垫与半导体晶片的第一侧接触，并且第二抛光垫与半导体晶片的第二面接触，使得第一和第二抛光垫相对定位。 心轴旋转以旋转晶片。

公开(公告)号：US6096659A

公开(公告)日：2000-08-01

申请号：US59159

申请日：1998-04-13

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21/033 ,  H01L21/00

CPC分类号： H01L21/0337 ,  H01L21/0338 ,  Y10S438/947 ,  Y10S438/95

摘要： A process for reducing dimensions of circuit elements in a semiconductor device. The process reduces feature sizes by using an intermediate etchable mask layer between a photo-resistive mask and a layer to be etched. The etchable mask layer below the photo-resistive mask is etched and portions remain which undercut the pattern on the photo-resistive mask. After removing the photo-resistive mask, the remaining mask portions are then used to mask the layer to be etched. By undercutting the photo-resistive mask, the mask portions form a pattern having features with widths that are less than widths of features in the photo-resistive mask. The layer to be etched can then be etched to provide circuit elements with reduced dimensions.

摘要翻译： 一种用于减小半导体器件中电路元件尺寸的方法。 该方法通过在光电阻掩模和待蚀刻层之间使用中间可蚀刻掩模层来降低特征尺寸。 蚀刻光电阻掩模下面的可蚀刻掩模层，并且保留部分保留在光阻掩模上的图案。 在去除光电阻掩模之后，然后使用剩余的掩模部分来掩蔽待蚀刻的层。 通过底切光电阻掩模，掩模部分形成具有宽度小于光阻掩模中的特征的宽度的特征的图案。 然后可以蚀刻待蚀刻的层以提供具有减小的尺寸的电路元件。

公开(公告)号：US6048766A

公开(公告)日：2000-04-11

申请号：US172410

申请日：1998-10-14

申请人： Mark I. Gardner ,  Mark C. Gilmer ,  Thomas E. Spikes, Jr.

发明人： Mark I. Gardner ,  Mark C. Gilmer ,  Thomas E. Spikes, Jr.

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  H01L21/336

CPC分类号： H01L29/516 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/511 ,  H01L21/28194

摘要： A memory device having a high performance stacked dielectric sandwiched between two polysilicon plates and method of fabrication thereof is provided. A memory device, in accordance with an embodiment, includes two polysilicon plates and a high permittivity dielectric stack disposed between the two polysilicon plates. The high permittivity dielectric stack includes a relatively high permittivity layer and two relatively low permittivity buffer layers. Each buffer layer is disposed between the relatively high permittivity layer and a respective one of the two polysilicon plates. The high permittivity layer may, for example, be a barium strontium titanate and the buffer layers may each include a layer of silicon nitride adjacent the respective polysilicon plate and a layer of titanium dioxide between the silicon nitride and the barium strontium titanate. The new high performance dielectric layer can, for example, increase the speed and reliability of the memory device as compared to conventional memory devices.

摘要翻译： 提供了一种具有夹在两个多晶硅板之间的高性能堆叠电介质的存储器件及其制造方法。 根据实施例的存储器件包括两个多晶硅板和设置在两个多晶硅板之间的高介电常数介电堆叠。 高介电常数介电堆叠包括相对较高的介电常数层和两个较低的介电常数缓冲层。 每个缓冲层设置在相对较高的介电常数层和两个多晶硅板的相应的一个之间。 高电容率层可以是例如钛酸锶钡，并且缓冲层可以各自包括邻近相应多晶硅板的氮化硅层和氮化硅和钛酸钡锶钛之间的二氧化钛层。 例如，与传统的存储器件相比，新的高性能介电层可以提高存储器件的速度和可靠性。

公开(公告)号：US6040207A

公开(公告)日：2000-03-21

申请号：US189278

申请日：1998-11-10

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L21/316

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28238 ,  H01L29/513 ,  H01L29/518 ,  H01L21/28211

摘要： A semiconductor process in which a silicon film is chemically vapor deposited upon a native oxide film as part of the gate oxide formation process. The invention contemplates a method of forming a thin gate dielectric semiconductor transistor. A semiconductor substrate which includes a native oxide film on an upper region of a silicon bulk is provided and a silicon film is deposited on the native oxide film. A first oxide film is then formed on a the native oxide film by thermally oxidizing a portion of the silicon film proximal to the native oxide film such that the thin gate dielectric comprises the native oxide film and the first oxide film. Thereafter, a conductive gate is formed on the thin gate dielectric and a pair of source/drain structures are formed within a pair of source/drain regions of the semiconductor substrate. The pair of source/drain structures are laterally displaced on either side of the channel region of the semiconductor substrate. In one embodiment the process further includes the step, prior to the formation of the first oxide layer, of thinning the silicon layer by removing an upper portion of the silicon layer. In one embodiment, a barrier dielectric is deposited on an upper surface of the silicon film prior to the step of forming the first oxide film. In still another embodiment, the process further includes the step of depositing a barrier dielectric after the formation of the first oxide film and prior to the formation of the conductive gate.

摘要翻译： 作为栅极氧化物形成工艺的一部分，将硅膜化学气相沉积在自然氧化膜上的半导体工艺。 本发明考虑了形成薄栅介质半导体晶体管的方法。 提供了包括硅体上部区域上的自然氧化膜的半导体衬底，并且在该自然氧化膜上沉积硅膜。 然后通过热氧化接近自然氧化膜的硅膜的一部分使得薄栅电介质包括天然氧化膜和第一氧化物膜，在自然氧化膜上形成第一氧化物膜。 此后，在薄栅极电介质上形成导电栅极，并且在半导体衬底的一对源极/漏极区域内形成一对源极/漏极结构。 一对源极/漏极结构在半导体衬底的沟道区的任一侧上被横向移位。 在一个实施例中，该方法还包括在形成第一氧化物层之前通过去除硅层的上部来使硅层变薄的步骤。 在一个实施例中，在形成第一氧化物膜的步骤之前，在硅膜的上表面上沉积阻挡电介质。 在另一个实施例中，该方法还包括在形成第一氧化物膜之后并且在形成导电栅极之前沉积阻挡电介质的步骤。

公开(公告)号：US5963810A

公开(公告)日：1999-10-05

申请号：US993414

申请日：1997-12-18

申请人： Mark I. Gardner ,  Mark C. Gilmer ,  Thomas E. Spikes, Jr.

发明人： Mark I. Gardner ,  Mark C. Gilmer ,  Thomas E. Spikes, Jr.

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/51

CPC分类号： H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66575

摘要： A semiconductor device having a nitrogen enhanced high permittivity gate insulating layer and a process for manufacturing such a device is provided. Consistent with one embodiment, a high permittivity gate insulating layer is formed over a substrate using a nitrogen bearing gas. The gate insulating layer has a dielectric constant of at least 20. At least one gate electrode is formed over the high permittivity gate insulating layer. An optional nitride capping layer can be formed between the high permittivity gate insulating layer and the gate electrode. The nitrogen bearing gas may include one or more nitrogen bearing species, such as NO, NF.sub.3 or N2, for example. The use of nitrogen in the formation of a high permittivity gate insulating layer can, for example, reduce oxidation of the high permittivity layer and increase the ability to control the characteristics of the gate insulating layer.

摘要翻译： 提供一种具有氮增强型高介电常数栅极绝缘层的半导体器件及其制造方法。 根据一个实施例，使用含氮气体在衬底上形成高介电常数栅极绝缘层。 栅极绝缘层的介电常数至少为20.在高介电常数栅极绝缘层上形成至少一个栅电极。 可以在高介电常数栅极绝缘层和栅电极之间形成任选的氮化物覆盖层。 含氮气体可以包括一种或多种含氮物质，例如NO，NF 3或N 2。 在形成高介电常数栅极绝缘层时使用氮可以例如降低高介电常数层的氧化并增加控制栅极绝缘层的特性的能力。

公开(公告)号：US5897358A

公开(公告)日：1999-04-27

申请号：US999577

申请日：1997-11-28

申请人： Mark I. Gardner ,  Mark C. Gilmer ,  Thomas E. Spikes, Jr.

发明人： Mark I. Gardner ,  Mark C. Gilmer ,  Thomas E. Spikes, Jr.

IPC分类号： H01L21/28 ,  H01L21/3105 ,  H01L21/336 ,  H01L29/417 ,  H01L29/49 ,  H01L29/51 ,  H01L21/20 ,  H01L21/36

CPC分类号： H01L21/28194 ,  H01L21/31051 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66568

摘要： A semiconductor device having a fluorine-enhanced transistor with elevated active regions and process for fabricating such a device is provided. A semiconductor device, consistent with one embodiment of the invention, includes a substrate and at least one pair of elevated active regions disposed on the substrate. A fluorine-bearing barrier layer is disposed over the substrate between the elevated active regions. A high permittivity layer is disposed over the barrier layer and between the elevated active regions. Finally, a gate electrode is disposed over the high permittivity layer. In some embodiments, a thin insulating layer is disposed between the gate electrode and the high permittivity layer. The thin insulating layer and the fluorine-bearing barrier layer may, for example, both be formed of a topaz, while the high permittivity layer may, for example, be formed from a manganese oxide.

摘要翻译： 提供一种具有提高的有源区的氟增强晶体管的半导体器件和用于制造这种器件的工艺。 与本发明的一个实施例一致的半导体器件包括衬底和设置在衬底上的至少一对升高的有源区。 含氟阻挡层设置在升高的活性区域之间的衬底上。 高介电常数层设置在阻挡层之上和升高的有源区之间。 最后，栅电极设置在高电容率层上。 在一些实施例中，薄绝缘层设置在栅电极和高介电常数层之间。 例如，薄绝缘层和含氟阻挡层可以由黄玉形成，而高介电常数层例如可以由氧化锰形成。

公开(公告)号：US5890269A

公开(公告)日：1999-04-06

申请号：US993339

申请日：1997-12-19

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： B65G49/07 ,  H01L21/68 ,  H01L21/687

CPC分类号： H01L21/68757 ,  H01L21/68 ,  H01L21/68785 ,  Y10S414/136 ,  Y10T29/41 ,  Y10T428/218 ,  Y10T428/24273 ,  Y10T428/24298

摘要： A semiconductor wafer comprising a single crystalline lattice suitable for use in the manufacture of integrated circuits, namely computer chips and dies, wherein a diameter of the wafer is greater than approximately 150 millimeters and wherein the wafer includes a first hole extending through the wafer. The hole is adapted to facilitate handling of the wafer without directly contacting a surface of the wafer. The wafer preferably includes a primary flat and the first hole includes a flat side having a predetermined and known orientation with respect to the primary flat of the wafer. In one embodiment, the wafer further includes a guide hole formed near the first hole such that the center-points of the first hole and the guide hole are oriented with a predetermined and known orientation with respect to the primary flat of the wafer.