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公开(公告)号：US20190324848A1
公开(公告)日：2019-10-24
申请号：US15958496
申请日：2018-04-20
Applicant: Micron Technology, Inc.
Inventor： Paolo Amato , Marco Sforzin
Abstract: Apparatuses and methods related to correcting errors can include using FD decoders and AD decoders. Correcting errors can include receiving input data from the memory array, performing a plurality of operations associated with an error detection on the input data, and providing, based on processing the input data, output data, a validation flag, and a plurality of parity bits to a second decoder hosted by a controller coupled to the memory device.
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公开(公告)号：US20190198096A1
公开(公告)日：2019-06-27
申请号：US15853328
申请日：2017-12-22
Applicant: Micron Technology, Inc.
Inventor： Graziano Mirichigni , Marco Sforzin , Alessandro Orlando
Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a certain number bits having a first logic state prior to storing the user data in memory cells. Subsequently, reading the encoded user data may be carried out by applying a read voltage to the memory cells while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. The auto-referenced read may identify a particular switching event that correlates to a median threshold voltage value of the subset of the memory cells. Then, the auto-referenced read may determine a reference voltage that takes into account a statistical property of threshold voltage distribution of the subset of the memory cells. The auto-referenced read may identify a time duration to maintain the read voltage based on determining the reference voltage. When the time duration expires, the auto-referenced read may determine that the memory cells that have been activated correspond to the first logic state.
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公开(公告)号：US20180366177A1
公开(公告)日：2018-12-20
申请号：US16110601
申请日：2018-08-23
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Paolo Amato
IPC: G11C11/406 , G11C16/34 , G11C16/10 , G05F3/26 , G11C16/04
Abstract: The present disclosure includes apparatuses and methods related to refresh in memory. An example apparatus can refresh an array of memory cells in response to a portion of memory cells in an array having threshold voltages that are greater than a reference voltage.
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公开(公告)号：US20160062831A1
公开(公告)日：2016-03-03
申请号：US14841372
申请日：2015-08-31
Applicant: Micron Technology, Inc.
Inventor： Christophe Laurent , Paolo Amato , Marco Sforzin , Corrado Villa
CPC classification number: G06F11/1068 , G11C29/52 , H03M13/2909
Abstract: A memory array and a method of writing to a unidirectional non-volatile storage cell are disclosed whereby a user data word is transformed to an internal data word and written to one or more unidirectional data storage cells according to a cell coding scheme. A check word may be generated that corresponds to the internal data word. In some embodiments, the check word may be generated by inverting one or more bits of an intermediate check word. Other embodiments may be described and claimed.
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公开(公告)号：US09177622B2
公开(公告)日：2015-11-03
申请号：US14524720
申请日：2014-10-27
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin
CPC classification number: G11C7/222 , G11C5/147 , G11C7/1066 , G11C7/1093 , H03H11/26
Abstract: Electronic apparatus, systems, and methods can include a delayer having an inverter chain, where each inverter of the chain can be operatively regulated using current generators to control variation of the delay time of the delayer. In various embodiments, current generators can be arranged to provide reference voltages to each inverter stage of an inverter chain. Additional apparatus, systems, and methods are disclosed.
Abstract translation: 电子设备，系统和方法可以包括具有逆变器链的延迟器，其中链的每个反相器可以使用电流发生器来可操作地调节，以控制延迟器的延迟时间的变化。 在各种实施例中，电流发生器可被布置成向逆变器链的每个逆变器级提供参考电压。 公开了附加装置，系统和方法。
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Patent Agency Ranking
公开(公告)号：US20150071012A1
公开(公告)日：2015-03-12
申请号：US14524720
申请日：2014-10-27
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin
CPC classification number: G11C7/222 , G11C5/147 , G11C7/1066 , G11C7/1093 , H03H11/26
Abstract: Electronic apparatus, systems, and methods can include a delayer having an inverter chain, where each inverter of the chain can be operatively regulated using current generators to control variation of the delay time of the delayer. In various embodiments, current generators can be arranged to provide reference voltages to each inverter stage of an inverter chain. Additional apparatus, systems, and methods are disclosed.
Abstract translation: 电子设备，系统和方法可以包括具有逆变器链的延迟器，其中链的每个反相器可以使用电流发生器来可操作地调节，以控制延迟器的延迟时间的变化。 在各种实施例中，电流发生器可被布置成向逆变器链的每个逆变器级提供参考电压。 公开了附加装置，系统和方法。
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公开(公告)号：US20250130720A1
公开(公告)日：2025-04-24
申请号：US18903468
申请日：2024-10-01
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Marco Sforzin , Emanuele Confalonieri
IPC: G06F3/06
Abstract: A system includes a memory device; and a processing device coupled to the memory device, the processing device to perform operations including: identifying at least one unusable management unit (UMU) in a plurality of management units that are designated for wear leveling; storing, in a data structure, a physical address and a logical address of the identified at least one UMU; excluding, from a physical address space for wear leveling, the physical address of the identified at least one UMU; and performing a wear leveling operation using the physical address space, wherein the wear leveling operation moves data of a management unit to a neighboring management unit in a circular manner.
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公开(公告)号：US20250094344A1
公开(公告)日：2025-03-20
申请号：US18782380
申请日：2024-07-24
Applicant: Micron Technology, Inc.
Inventor： Rishabh Dubey , Marco Sforzin , Emanuele Confalonieri , Danilo Caraccio , Daniele Balluchi , Nicola Del Gatto
Abstract: A variety of applications can include a memory device having chained mapping with compression of received data. The memory device can include a mapping table having an entry location to associate a virtual page with a physical address of a first stripe of compressed data of the virtual page. A controller of the memory device, responsive to the data of the virtual page being compressed data, can load information about a second stripe of the compressed data into extra locations in the first stripe different from locations for compressed data of the virtual page in the first stripe. Additional apparatus, systems, and methods are disclosed.
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公开(公告)号：US12189478B2
公开(公告)日：2025-01-07
申请号：US17828475
申请日：2022-05-31
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Paolo Amato , Daniele Balluchi
IPC: G06F11/10
Abstract: A system and method for memory error recovery in compute express link (CXL) components is presented. The method includes determining that a memory component has sustained a hard failure in a Cyclic Redundancy Check-Redundant Array of Independent Devices (CRC-RAID) mechanism. The method further includes determining a location of the memory component failure, wherein the CRC-RAID mechanism comprises a plurality of memory components configured as a plurality of stripes and initiates a write operation of user data to a location within a particular stripe, wherein the particular stripe contains a failed memory component. The method includes compensating for the failed memory component, wherein the compensating comprises a plurality of read operations prior to a writing of the user data.
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公开(公告)号：US20240428863A1
公开(公告)日：2024-12-26
申请号：US18821501
申请日：2024-08-30
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Riccardo Muzzetto
Abstract: The present disclosure includes apparatuses, methods, and systems for balancing data in memory. An embodiment includes a memory having a group of memory cells, wherein each respective memory cell is programmable to one of three possible data states, and circuitry to balance data programmed to the group between the three possible data states by determining whether the data programmed to the group is balanced for any one of the three possible data states, and upon determining the data programmed to the group is not balanced for any one of the three possible data states apply a rotational mapping algorithm to the data programmed to the group until the data is balanced for any one of the three possible data states and apply a Knuth algorithm to the data of the group programmed to the two of the three possible data states that were not balanced by the rotational mapping algorithm.
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