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    APPARATUSES AND METHODS FOR PERFORMING CORNER TURN OPERATIONS USING SENSING CIRCUITRY
    71.
    发明申请
    APPARATUSES AND METHODS FOR PERFORMING CORNER TURN OPERATIONS USING SENSING CIRCUITRY 审中-公开

    公开(公告)号：US20190108863A1

    公开(公告)日：2019-04-11

    申请号：US16215122

    申请日：2018-12-10

    Applicant: Micron Technology, Inc.

    Inventor： Jason T. Zawodny ,  Sanjay Tiwari

    IPC: G11C7/06 ,  G11C15/04 ,  G11C8/10 ,  G11C8/16

    CPC classification number: G11C7/065 ,  G11C8/10 ,  G11C8/16 ,  G11C15/043

    Abstract: The present disclosure includes apparatuses and methods related to performing corner turn operations using sensing circuitry. An example apparatus comprises a first group of memory cells coupled to an access line and a plurality of sense lines and a second group of memory cells coupled to a plurality of access lines and one of the plurality of sense lines. The access line can be a same access line as one of the plurality of access lines. The example apparatus comprises a controller configured to cause a corner turn operation on an element stored in the first group of memory cells resulting in the element being stored in the second group of memory cells to be performed using sensing circuitry.

    Apparatuses and methods for performing corner turn operations using sensing circuitry
    72.
    发明授权
    Apparatuses and methods for performing corner turn operations using sensing circuitry 有权

    公开(公告)号：US10153008B2

    公开(公告)日：2018-12-11

    申请号：US15133986

    申请日：2016-04-20

    Applicant: Micron Technology, Inc.

    Inventor： Jason T. Zawodny ,  Sanjay Tiwari

    IPC: G11C7/10 ,  G11C7/06 ,  G11C8/16 ,  G11C8/10

    Abstract: The present disclosure includes apparatuses and methods related to performing corner turn operations using sensing circuitry. An example apparatus comprises a first group of memory cells coupled to an access line and a plurality of sense lines and a second group of memory cells coupled to a plurality of access lines and one of the plurality of sense lines. The access line can be a same access line as one of the plurality of access lines. The example apparatus comprises a controller configured to cause a corner turn operation on an element stored in the first group of memory cells resulting in the element being stored in the second group of memory cells to be performed using sensing circuitry.

    Signed element compare in memory
    75.
    发明授权
    Signed element compare in memory 有权

    公开(公告)号：US10043570B1

    公开(公告)日：2018-08-07

    申请号：US15489442

    申请日：2017-04-17

    Applicant: Micron Technology, Inc.

    Inventor： Sanjay Tiwari

    IPC: G11C11/40 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4076 ,  G11C11/16

    CPC classification number: G11C11/4091 ,  G11C7/1006 ,  G11C11/1673 ,  G11C11/4076 ,  G11C11/4096

    Abstract: Examples of the present disclosure provide apparatuses and methods for performing signed element compare operations. An apparatus can include a first group of memory cells coupled to a sense line and to a number of first access lines. The apparatus can include a second group of memory cells coupled to the sense line and to a number of second access lines. The apparatus can include a controller configured to operate sensing circuitry to perform a number of operations to compare a value of a first signed element stored in the first group of memory cells to a value of a second signed element stored in the second group of memory cells.

    Data gathering in memory
    76.
    发明授权
    Data gathering in memory 有权

    公开(公告)号：US10026459B2

    公开(公告)日：2018-07-17

    申请号：US15692783

    申请日：2017-08-31

    Applicant: Micron Technology, Inc.

    Inventor： Jason T. Zawodny ,  Sanjay Tiwari ,  Richard C. Murphy

    IPC: G11C5/06 ,  G11C7/10

    CPC classification number: G11C7/1012 ,  G11C5/06 ,  G11C5/066 ,  G11C7/1006 ,  G11C11/4091

    Abstract: Examples of the present disclosure provide apparatuses and methods for storing a first element in memory cells coupled to a first sense line and a plurality of access line. The examples can include storing a second element in memory cells coupled to a second sense line and the plurality of access lines. The memory cells coupled to the first sense line can be separated from the memory cells coupled to the second sense line by at least memory cells coupled to a third sense line and the plurality of access lines. The examples can include storing the second element in the memory cells coupled to the third sense line.

    MULTIPLICATION OPERATIONS IN MEMORY
    77.
    发明申请
    MULTIPLICATION OPERATIONS IN MEMORY 审中-公开

    公开(公告)号：US20180189031A1

    公开(公告)日：2018-07-05

    申请号：US15905083

    申请日：2018-02-26

    Applicant: Micron Technology, Inc.

    Inventor： Sanjay Tiwari

    IPC: G06F7/523 ,  G11C7/10

    CPC classification number: G06F7/523 ,  G06F7/53 ,  G06G7/16 ,  G11C7/1006 ,  G11C11/4091 ,  H03K19/17732

    Abstract: Examples of the present disclosure provide apparatuses and methods for performing multi-variable bit-length multiplication operations in a memory. An example method comprises performing a multiplication operation on a first vector and a second vector. The first vector includes a number of first elements stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array. The second vector includes a number of second elements stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The example multiplication operation can include performing a number of AND operations, OR operations and SHIFT operations without transferring data via an input/output (I/O) line.

    SMALLEST OR LARGEST VALUE ELEMENT DETERMINATION
    78.
    发明申请
    SMALLEST OR LARGEST VALUE ELEMENT DETERMINATION 审中-公开

    公开(公告)号：US20180046461A1

    公开(公告)日：2018-02-15

    申请号：US15237085

    申请日：2016-08-15

    Applicant: Micron Technology, Inc.

    Inventor： Sanjay Tiwari

    IPC: G06F9/30

    CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/30021 ,  G06F9/3004 ,  G06F15/785

    Abstract: Examples of the present disclosure provide apparatuses and methods for smallest value element or largest value element determination in memory. An example method comprises: storing an elements vector comprising a plurality of elements in a group of memory cells coupled to an access line of an array; performing, using sensing circuitry coupled to the array, a logical operation using a first vector and a second vector as inputs, with a result of the logical operation being stored in the array as a result vector; updating the result vector responsive to performing a plurality of subsequent logical operations using the sensing circuitry; and providing an indication of which of the plurality of elements have one of a smallest value and a largest value.

    Data gathering in memory
    79.
    发明授权
    Data gathering in memory 有权

    公开(公告)号：US09892767B2

    公开(公告)日：2018-02-13

    申请号：US15043236

    申请日：2016-02-12

    Applicant: Micron Technology, Inc.

    Inventor： Jason T. Zawodny ,  Sanjay Tiwari ,  Richard C. Murphy

    IPC: G11C5/06 ,  G11C7/10

    CPC classification number: G11C7/1012 ,  G11C5/06 ,  G11C5/066 ,  G11C7/1006 ,  G11C11/4091

    Abstract: Examples of the present disclosure provide apparatuses and methods for storing a first element in memory cells coupled to a first sense line and a plurality of access line. The examples can include storing a second element in memory cells coupled to a second sense line and the plurality of access lines. The memory cells coupled to the first sense line can be separated from the memory cells coupled to the second sense line by at least memory cells coupled to a third sense line and the plurality of access lines. The examples can include storing the second element in the memory cells coupled to the third sense line.

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