公开(公告)号：US20100052146A1

公开(公告)日：2010-03-04

申请号：US12616834

申请日：2009-11-12

申请人： Yih-Jenn Jiang ,  Han-Ping Pu ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

发明人： Yih-Jenn Jiang ,  Han-Ping Pu ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/522 ,  H01L21/56

CPC分类号： H01L23/3121 ,  H01L21/561 ,  H01L21/6835 ,  H01L24/48 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and a fabrication method are disclosed. The fabrication method includes applying a sacrificial layer on one surface of a metal carrier, applying an insulation layer on the sacrificial layer, and forming through holes in the sacrificial layer and the insulation layer to expose the metal carrier; forming a conductive metallic layer in each through hole; forming a patterned circuit layer on the insulation layer to be electrically connected to the conductive metallic layer; mounting at least a chip on the insulation layer and electrically connecting the chip to the patterned circuit layer; forming an encapsulant to encapsulate the chip and the patterned circuit layer; and removing the metal carrier and the sacrificial layer to expose the insulation layer and conductive metallic layer to allow the conductive metallic layer to protrude from the insulation layer. In the present invention, the distance between the semiconductor package and the external device is increased, and thermal stress caused by difference between the thermal expansion coefficients is reduced, so as to enhance the reliability of the product.

摘要翻译： 公开了半导体封装和制造方法。 制造方法包括在金属载体的一个表面上施加牺牲层，在牺牲层上施加绝缘层，以及在牺牲层和绝缘层中形成通孔以露出金属载体; 在每个通孔中形成导电金属层; 在所述绝缘层上形成图案化电路层，以电连接到所述导电金属层; 将至少一个芯片安装在所述绝缘层上并将所述芯片电连接到所述图案化电路层; 形成密封剂以封装所述芯片和所述图案化电路层; 并且去除金属载体和牺牲层以暴露绝缘层和导电金属层，以允许导电金属层从绝缘层突出。 在本发明中，半导体封装和外部器件之间的距离增加，由于热膨胀系数之差导致的热应力降低，从而提高了产品的可靠性。

公开(公告)号：US07485496B2

公开(公告)日：2009-02-03

申请号：US11648443

申请日：2006-12-29

申请人： Kun-Sheng Chien ,  Shih-Kuang Chiu ,  Han-Ping Pu ,  Cheng-Hsu Hsiao

发明人： Kun-Sheng Chien ,  Shih-Kuang Chiu ,  Han-Ping Pu ,  Cheng-Hsu Hsiao

IPC分类号： H01L21/00

CPC分类号： H01L23/3675 ,  H01L21/4871 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/16251

摘要： A semiconductor package with a heat sink and a method for fabricating the same are proposed. A first adhesive of a low Young's modulus is disposed on a corner region of a heat sink mounting area of a substrate. A second adhesive of a high Young's modulus is disposed on the heat sink mounting area except the corner region. The heat sink is mounted on the heat sink mounting area and thereby secured in position to the substrate, by the first and second adhesives. The disposition of the first and second adhesives of different Young's moduli not only prevents detachment of the heat sink from the substrate, but also controls the flatness of the heat sink. The prevent invention does not affect the appearance of the semiconductor package and its ensuing assembly process.

摘要翻译： 提出了具有散热器的半导体封装及其制造方法。 低杨氏模量的第一粘合剂设置在基板的散热器安装区域的拐角区域。 高杨氏模量的第二粘合剂设置在除了拐角区域之外的散热器安装区域上。 散热器安装在散热器安装区域上，从而通过第一和第二粘合剂固定到基板上。 不同杨氏模量的第一和第二粘合剂的配置不仅防止散热器从基板脱离，而且还控制散热器的平坦度。 防止发明不影响半导体封装的外观及其随后的组装过程。

公开(公告)号：US20080224283A1

公开(公告)日：2008-09-18

申请号：US11523719

申请日：2006-09-20

申请人： Han-Ping Pu ,  Chien-Ping Huang

发明人： Han-Ping Pu ,  Chien-Ping Huang

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L24/13 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/4951 ,  H01L23/49548 ,  H01L24/14 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/13099 ,  H01L2224/14 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014

摘要： A leadframe-based semiconductor package and a fabrication method thereof are provided. The leadframe-based semiconductor package includes a chip implanted with a plurality of first and second conductive bumps thereon, and a leadframe having a plurality of leads. The first conductive bumps are bonded to the leads to electrically connect the chip to the leadframe. The chip, the first and second conductive bumps, and the leadframe are encapsulated by an encapsulant, with bottom ends of the second conductive bumps and bottom surfaces of the leads being exposed from the encapsulant. This allows the second conductive bumps to provide additional input/output electrical connections for the chip besides the leads.

摘要翻译： 提供了一种引线框半导体封装及其制造方法。 基于引线框的半导体封装包括在其上注入多个第一和第二导电凸块的芯片以及具有多个引线的引线框架。 第一导电凸块被接合到引线以将芯片电连接到引线框架。 芯片，第一和第二导电凸块和引线框架由密封剂封装，第二导电凸块的底端和引线的底表面从密封剂暴露出来。 这允许第二导电凸块除了引线之外为芯片提供额外的输入/输出电连接。

公开(公告)号：US20080116580A1

公开(公告)日：2008-05-22

申请号：US11985662

申请日：2007-11-16

申请人： Yih-Jenn Jiang ,  Han-Ping Pu ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

发明人： Yih-Jenn Jiang ,  Han-Ping Pu ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/48 ,  H01L21/56

CPC分类号： H01L23/3121 ,  H01L21/561 ,  H01L21/6835 ,  H01L24/48 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and a fabrication method are disclosed. The fabrication method includes applying a sacrificial layer on one surface of a metal carrier, applying an insulation layer on the sacrificial layer, and forming through holes in the sacrificial layer and the insulation layer to expose the metal carrier; forming a conductive metallic layer in each through hole; forming a patterned circuit layer on the insulation layer to be electrically connected to the conductive metallic layer; mounting at least a chip on the insulation layer and electrically connecting the chip to the patterned circuit layer; forming an encapsulant to encapsulate the chip and the patterned circuit layer; and removing the metal carrier and the sacrificial layer to expose the insulation layer and conductive metallic layer to allow the conductive metallic layer to protrude from the insulation layer. In the present invention, the distance between the semiconductor package and the external device is increased, and thermal stress caused by difference between the thermal expansion coefficients is reduced, so as to enhance the reliability of the product.

摘要翻译： 公开了半导体封装和制造方法。 制造方法包括在金属载体的一个表面上施加牺牲层，在牺牲层上施加绝缘层，以及在牺牲层和绝缘层中形成通孔以露出金属载体; 在每个通孔中形成导电金属层; 在所述绝缘层上形成图案化电路层，以电连接到所述导电金属层; 将至少一个芯片安装在所述绝缘层上并将所述芯片电连接到所述图案化电路层; 形成密封剂以封装所述芯片和所述图案化电路层; 并且去除金属载体和牺牲层以暴露绝缘层和导电金属层，以允许导电金属层从绝缘层突出。 在本发明中，半导体封装和外部器件之间的距离增加，由于热膨胀系数之差导致的热应力降低，从而提高了产品的可靠性。

公开(公告)号：US20070284710A1

公开(公告)日：2007-12-13

申请号：US11891926

申请日：2007-08-14

申请人： Chi-Chuan Wu ,  Chien-Ping Huang ,  Han-Ping Pu

发明人： Chi-Chuan Wu ,  Chien-Ping Huang ,  Han-Ping Pu

IPC分类号： H01L23/495 ,  H01L21/00

CPC分类号： H01L24/16 ,  H01L23/4951 ,  H01L23/49558 ,  H01L23/49575 ,  H01L2224/13099 ,  H01L2224/16245 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00

摘要： A flip-ship semiconductor package with a lead frame as a chip carrier is provided, wherein a plurality of leads of the lead frame are each formed with at least a dam member thereon. When a chip is mounted on the lead frame by means of solder bumps, each of the solder bumps is attached to the corresponding one of the leads at a position between the dam member and an inner end of the lead. During a reflow-soldering process for wetting the solder bumps to the leads, the dam members would help control collapse height of the solder bumps, so as to enhance resistance of the solder bumps to thermal stress generated by CTE (coefficient of thermal expansion) mismatch between the chip and the leads, thereby preventing incomplete electrical connection between the chip and the leads.

摘要翻译： 提供一种具有引线框架作为芯片载体的翻转半导体封装，其中引线框架的多个引线至少形成有至少一个阻挡构件。 当通过焊料凸块将芯片安装在引线框架上时，每个焊料凸块在引线的阻挡件和引线的内端之间的位置附接到相应的一个引线。 在用于将焊料凸点润湿到引线的回流焊接过程中，阻挡构件将有助于控制焊料凸块的塌陷高度，从而增强焊料凸块对CTE产生的热应力的阻力（热膨胀系数）不匹配 在芯片和引线之间，从而防止芯片和引线之间的不完全的电连接。

公开(公告)号：US20070235861A1

公开(公告)日：2007-10-11

申请号：US11648443

申请日：2006-12-29

申请人： Kun-Sheng Chien ,  Shih-Kuang Chiu ,  Han-Ping Pu ,  Cheng-Hsu Hsiao

发明人： Kun-Sheng Chien ,  Shih-Kuang Chiu ,  Han-Ping Pu ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/34 ,  H01L21/00

CPC分类号： H01L23/3675 ,  H01L21/4871 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/16251

摘要： A semiconductor package with a heat sink and a method for fabricating the same are proposed. A first adhesive of a low Young's modulus is disposed on a corner region of a heat sink mounting area of a substrate. A second adhesive of a high Young's modulus is disposed on the heat sink mounting area except the corner region. The heat sink is mounted on the heat sink mounting area and thereby secured in position to the substrate, by the first and second adhesives. The disposition of the first and second adhesives of different Young's moduli not only prevents detachment of the heat sink from the substrate, but also controls the flatness of the heat sink. The prevent invention does not affect the appearance of the semiconductor package and its ensuing assembly process.

摘要翻译： 提出了具有散热器的半导体封装及其制造方法。 低杨氏模量的第一粘合剂设置在基板的散热器安装区域的拐角区域。 高杨氏模量的第二粘合剂设置在除了拐角区域之外的散热器安装区域上。 散热器安装在散热器安装区域上，从而通过第一和第二粘合剂固定到基板上。 不同杨氏模量的第一和第二粘合剂的配置不仅防止散热器从基板脱离，而且还控制散热器的平坦度。 防止发明不影响半导体封装的外观及其随后的组装过程。

公开(公告)号：US20070181990A1

公开(公告)日：2007-08-09

申请号：US11591974

申请日：2006-11-01

申请人： Chien-Ping Huang ,  Chih-Ming Huang ,  Han-Ping Pu ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

发明人： Chien-Ping Huang ,  Chih-Ming Huang ,  Han-Ping Pu ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/02 ,  H01L21/00

CPC分类号： H01L23/3128 ,  H01L21/561 ,  H01L21/565 ,  H01L23/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stacked semiconductor structure and fabrication method thereof are provided. The method includes mounting and connecting electrically a semiconductor chip to a first substrate, mounting on the first substrate a plurality of supporting members corresponding in position to a periphery of the semiconductor chip, mounting a second substrate having a first surface partially covered with a tape and a second surface opposite to the first surface on the supporting members via the second surface, connecting electrically the first and second substrates by bonding wires, forming on the first substrate an encapsulant for encapsulating the semiconductor chip, the supporting members, the second substrate, the bonding wires, and the tape with an exposed top surface, and removing the tape to expose the first surface of the second substrate and allow an electronic component to be mounted thereon. The present invention prevents reflow-induced contamination, spares a special mold, and eliminates flash.

摘要翻译： 提供了堆叠半导体结构及其制造方法。 该方法包括将半导体芯片电连接到第一基板上，在第一基板上安装多个对应于半导体芯片的周边的支撑部件，安装第二基板，该第二基板具有部分被带覆盖的第一表面， 经由第二表面与支撑构件上的第一表面相对的第二表面，通过接合线电连接第一和第二基板，在第一基板上形成用于封装半导体芯片的密封剂，支撑构件，第二基板， 接合线和具有暴露的顶表面的带，并且移除带以露出第二基板的第一表面并允许电子部件安装在其上。 本发明防止回流引起的污染，备有特殊的模具，并消除闪光。

公开(公告)号：US07208825B2

公开(公告)日：2007-04-24

申请号：US11125886

申请日：2005-05-09

申请人： Han-Ping Pu ,  Chien Ping Huang

发明人： Han-Ping Pu ,  Chien Ping Huang

IPC分类号： H01L23/48 ,  H01L23/02 ,  H01L23/52 ,  H01L23/28 ,  H01L23/31

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/24 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/1035 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor package and a fabrication method thereof are provided in which a chip is mounted on a substrate, and a dielectric layer is applied over the substrate and chip, with bond fingers formed on the substrate and electric contacts formed on the chip being exposed outside. A metal layer is formed over the dielectric layer and the exposed bond fingers and electric contacts, and patterned to form a plurality of conductive traces that electrically connect the electric contacts of the chip to the bond fingers of the substrate. The conductive traces replace conventional wire bonding technology and thus eliminate the occurrence of wire sweep or short circuits in fabrication processes. Therefore, a low profile chip with a reduced pitch between adjacent electric contacts can be used without being limited to feasibility of the wire bonding technology.

摘要翻译： 提供了一种半导体封装及其制造方法，其中芯片安装在基板上，并且电介质层被施加在基板和芯片上，具有形成在基板上的结合指状物，并且形成在芯片上的电触点暴露在外部。 在电介质层和暴露的结合指状物和电触点之上形成金属层，并且被图案化以形成将芯片的电触头电连接到衬底的结合指的多个导电迹线。 导电迹线取代了传统的引线键合技术，从而消除了制造工艺中线扫或短路的发生。 因此，可以使用在相邻的电触点之间具有减小的间距的低轮廓芯片，而不限于引线接合技术的可行性。

公开(公告)号：US07023085B2

公开(公告)日：2006-04-04

申请号：US10921582

申请日：2004-08-18

申请人： Han-Ping Pu

发明人： Han-Ping Pu

IPC分类号： H01L23/34

CPC分类号： H01L24/81 ,  H01L23/642 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/30105 ,  Y10S257/924 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor package structure for improving electrical performance and a method for fabricating the same are proposed, in which a substrate having at least one pair of passive component pads is provided, wherein a semiconductor chip is attached on the substrate and a passive component is mounted to the passive component pads to locate between the substrate and the semiconductor chip. Thus, the passive component can electrically connect the chip and the substrate simultaneously without arranging an additional conductive trace layer, thereby improving the electrical performance of the semiconductor package structure and reducing the structure size.

摘要翻译： 提出了一种用于提高电性能的半导体封装结构及其制造方法，其中提供具有至少一对无源元件焊盘的衬底，其中半导体芯片附着在衬底上，并且将无源元件安装到 无源元件焊盘位于衬底和半导体芯片之间。 因此，无源部件可以同时电连接芯片和基板，而不需要设置附加的导电迹线层，从而提高半导体封装结构的电气性能并降低结构尺寸。

公开(公告)号：US20050205978A1

公开(公告)日：2005-09-22

申请号：US11125886

申请日：2005-05-09

申请人： Han-Ping Pu ,  Chien Huang

发明人： Han-Ping Pu ,  Chien Huang

IPC分类号： H01L21/60 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L23/02

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/24 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/1035 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor package and a fabrication method thereof are provided in which a chip is mounted on a substrate, and a dielectric layer is applied over the substrate and chip, with bond fingers formed on the substrate and electric contacts formed on the chip being exposed outside. A metal layer is formed over the dielectric layer and the exposed bond fingers and electric contacts, and patterned to form a plurality of conductive traces that electrically connect the electric contacts of the chip to the bond fingers of the substrate. The conductive traces replace conventional wire bonding technology and thus eliminate the occurrence of wire sweep or short circuits in fabrication processes. Therefore, a low profile chip with a reduced pitch between adjacent electric contacts can be used without being limited to feasibility of the wire bonding technology.