公开(公告)号：US07781264B2

公开(公告)日：2010-08-24

申请号：US11891926

申请日：2007-08-14

申请人： Chi-Chuan Wu ,  Chien-Ping Huang ,  Han-Ping Pu

发明人： Chi-Chuan Wu ,  Chien-Ping Huang ,  Han-Ping Pu

IPC分类号： H01L21/44 ,  H01L21/48

CPC分类号： H01L24/16 ,  H01L23/4951 ,  H01L23/49558 ,  H01L23/49575 ,  H01L2224/13099 ,  H01L2224/16245 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00

摘要： A flip-ship semiconductor package with a lead frame as a chip carrier is provided, wherein a plurality of leads of the lead frame are each formed with at least a dam member thereon. When a chip is mounted on the lead frame by means of solder bumps, each of the solder bumps is attached to the corresponding one of the leads at a position between the dam member and an inner end of the lead. During a reflow-soldering process for wetting the solder bumps to the leads, the dam members would help control collapse height of the solder bumps, so as to enhance resistance of the solder bumps to thermal stress generated by CTE (coefficient of thermal expansion) mismatch between the chip and the leads, thereby preventing incomplete electrical connection between the chip and the leads.

摘要翻译： 提供一种具有引线框架作为芯片载体的翻转半导体封装，其中引线框架的多个引线至少形成有至少一个阻挡构件。 当通过焊料凸块将芯片安装在引线框架上时，每个焊料凸块在引线的阻挡件和引线的内端之间的位置附接到相应的一个引线。 在用于将焊料凸点润湿到引线的回流焊接过程中，阻挡构件将有助于控制焊料凸块的塌陷高度，从而增强焊料凸块对CTE产生的热应力的阻力（热膨胀系数）不匹配 在芯片和引线之间，从而防止芯片和引线之间的不完全的电连接。

公开(公告)号：US07274088B2

公开(公告)日：2007-09-25

申请号：US10196305

申请日：2002-07-16

申请人： Chi-Chuan Wu ,  Chien-Ping Huang ,  Han-Ping Pu

发明人： Chi-Chuan Wu ,  Chien-Ping Huang ,  Han-Ping Pu

IPC分类号： H01L23/495 ,  H01L29/40

CPC分类号： H01L24/16 ,  H01L23/4951 ,  H01L23/49558 ,  H01L23/49575 ,  H01L2224/13099 ,  H01L2224/16245 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00

摘要： A flip-ship semiconductor package with a lead frame as a chip carrier is provided, wherein a plurality of leads of the lead frame are each formed with at least a dam member thereon. When a chip is mounted on the lead frame by means of solder bumps, each of the solder bumps is attached to the corresponding one of the leads at a position between the dam member and an inner end of the lead. During a reflow-soldering process for wetting the solder bumps to the leads, the dam members would help control collapse height of the solder bumps, so as to enhance resistance of the solder bumps to thermal stress generated by CTE (coefficient of thermal expansion) mismatch between the chip and the leads, thereby preventing incomplete electrical connection between the chip and the leads.

摘要翻译： 提供一种具有引线框架作为芯片载体的翻转半导体封装，其中引线框架的多个引线至少形成有至少一个阻挡构件。 当通过焊料凸块将芯片安装在引线框架上时，每个焊料凸块在引线的阻挡件和引线的内端之间的位置附接到相应的一个引线。 在用于将焊料凸点润湿到引线的回流焊接过程中，阻挡构件将有助于控制焊料凸块的塌陷高度，从而增强焊料凸块对CTE产生的热应力的阻力（热膨胀系数）不匹配 在芯片和引线之间，从而防止芯片和引线之间的不完全的电连接。

公开(公告)号：US06949413B2

公开(公告)日：2005-09-27

申请号：US10389138

申请日：2003-03-13

申请人： Randy H. Y. Lo ,  Chi-Chuan Wu

发明人： Randy H. Y. Lo ,  Chi-Chuan Wu

IPC分类号： H01L21/56 ,  H01L23/31 ,  H01L23/433 ,  H01L21/50

CPC分类号： H01L23/3128 ,  H01L21/561 ,  H01L21/565 ,  H01L23/4334 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

摘要： A method is proposed for fabricating a TFBGA (Thin & Fine Ball-Grid Array) package with embedded heat spreader. Conventionally, since an individual TFBGA package is quite small in size, it would be highly difficult to incorporate an embedded heat spreader therein. As a solution to this problem, the proposed method utilizes a single substrate predefined with a plurality of package sites, and further utilizes a heat-spreader frame including an integrally-formed matrix of heat spreaders each corresponding to one of the package sites on the substrate. A batch of semiconductor chips are then mounted on the respective package sites on the substrate. During the encapsulation process, a single continuous encapsulation body is formed to encapsulate the entire heat-spreader frame and all the semiconductor chips. After ball implantation, a singulation process is performed to cut apart the encapsulation body into individual package units, each serving as the intended TFBGA package. In the foregoing process, since the entirety of the heat-spreader frame is relatively large in size as compared to the size of an individual TFBGA package, it can be easily handled, so that the embedding of a heat spreader in each package unit can be easily carried out.

公开(公告)号：US06764880B2

公开(公告)日：2004-07-20

申请号：US10456251

申请日：2003-06-05

申请人： Chi-Chuan Wu ,  Chien-Ping Huang

发明人： Chi-Chuan Wu ,  Chien-Ping Huang

IPC分类号： H01L2148

CPC分类号： H01L24/33 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/06135 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/484 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/85181 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A QFN semiconductor package and a fabrication method thereof are proposed, wherein a lead frame having a plurality of leads is adopted, and each lead is formed at its inner end with a protruding portion. A wire bonding region and a bump attach region are respectively defined on opposite surfaces of the protruding portion, and staggered in position. This allows a force applied from a wire bonder to the wire bonding regions not to adversely affect solder bumps implanted on the bump attach regions, so that the solder bumps can be structurally assured without cracking. Moreover, the wire bonding regions spaced apart from the bump attach regions can be prevented from being contaminated by an etching solution used in solder bump implantation, so that wire bonding quality can be well maintained.

摘要翻译： 提出了一种QFN半导体封装及其制造方法，其中采用具有多个引线的引线框架，并且每个引线的内端形成有突出部分。 引线接合区域和突起附着区域分别限定在突出部分的相对表面上并且交错位置。 这允许从引线接合器施加到引线接合区域的力不会不利地影响注入在凸块附接区域上的焊料凸起，使得焊料凸块可以在结构上确保而不会破裂。 此外，可以防止与凸块附接区域间隔开的引线接合区域被焊料凸块注入中使用的蚀刻溶液污染，从而可以良好地保持引线接合质量。

公开(公告)号：US06538321B2

公开(公告)日：2003-03-25

申请号：US09946999

申请日：2001-09-05

申请人： Chien-Ping Huang ,  Chi-Chuan Wu ,  Jui-Yu Chuang ,  Lien-Chi Chan

发明人： Chien-Ping Huang ,  Chi-Chuan Wu ,  Jui-Yu Chuang ,  Lien-Chi Chan

IPC分类号： H01L2310

CPC分类号： H01L23/4334 ,  H01L21/565 ,  H01L23/3121 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012

摘要： A heat sink with a collapse structure and a semiconductor device with the heat sink are proposed, in which the heat sink is in ladder-like shape due to a height difference formed between an extending portion and an body of the heat sink, and the body has at least one surface exposed to outside of the semiconductor package. The extending portion produces collapse deformation in response to stress from engagement of molds in a molding process, so as to prevent a semiconductor chip from being damaged by the stress. The heat sink directly attached to the chip allows heat generated by the chip to pass through the extending portion to the body of the heat sink, and then the heat can be dissipated through the exposed surface of the body to the outside of the semiconductor package, so as to improve the heat dissipating efficiency.

公开(公告)号：US06507098B1

公开(公告)日：2003-01-14

申请号：US09417409

申请日：1999-10-13

申请人： Randy H. Y. Lo ,  Chi-Chuan Wu

发明人： Randy H. Y. Lo ,  Chi-Chuan Wu

IPC分类号： H01L2302

CPC分类号： H01L25/0652 ,  H01L24/73 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/1515 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

摘要： A multi-chip packaging structure in which a plurality of chips is aligned on two surfaces of a substrate and the substrate has an opening. The chip located on the second surface of the substrate has center bonding pads arrangement. These bonding pads are connected to the conductive connections on the first surface of the substrate by means of the opening. The other chips are attached to the first surface of the substrate and have a plurality of bonding pads connected to the conductive connections on the first surface of the substrate by wire bonding or flip-chip bonding. Furthermore, a heat sink is attached to the back surface of the chip located on the second surface in order to improve the heat dissipation performance of the package.

摘要翻译： 一种多芯片封装结构，其中多个芯片对准在基板的两个表面上，并且该基板具有开口。 位于基板的第二表面上的芯片具有中心焊盘布置。 这些接合焊盘通过开口连接到衬底的第一表面上的导电连接。 其它芯片附接到基板的第一表面，并且具有通过引线接合或倒装芯片接合连接到基板的第一表面上的导电连接的多个焊盘。 此外，为了提高封装的散热性能，将散热器安装在位于第二表面上的芯片的背面。

公开(公告)号：US06414384B1

公开(公告)日：2002-07-02

申请号：US09746793

申请日：2000-12-22

申请人： Randy H. Y. Lo ,  Chien-Ping Huang ,  Chi-Chuan Wu

发明人： Randy H. Y. Lo ,  Chien-Ping Huang ,  Chi-Chuan Wu

IPC分类号： H01L2302

CPC分类号： H01L24/32 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A package structure stacking chips on a front surface and a back surface of a substrate including at least a substrate, a plurality of chip sets, a plurality of support members, a plurality of glue layers, a plurality of wires, and a mold compound. The substrate has a front surface and a back surface opposite to the front surface. Each chip set has one or more chips, each chip having a plurality of bonding pads. The chip sets are stacked as a laminate on the front surface of the substrate, respectively. A plurality of support members are arranged between each two adjacent chip sets. A glue layers are used to connect the support members, the chip sets, and the substrate. The chip in the same chip sets is electrically connected to each other or to the substrate by the bonding pads. Finally, the front surface of the substrate, the support members, the chip sets, and the glue layers are encapsulated with a mold compound. Moreover, a plurality of flip chips are deposited on the back surface of the substrate.

摘要翻译： 一种封装结构，其在至少包括基板，多个芯片组，多个支撑部件，多个胶合层，多个导线和模具化合物的基板的前表面和背面上堆叠芯片。 基板具有与前表面相对的前表面和后表面。 每个芯片组具有一个或多个芯片，每个芯片具有多个焊盘。 芯片组分别作为层叠体堆叠在基板的前表面上。 在每个两个相邻的芯片组之间布置有多个支撑构件。 使用胶层来连接支撑部件，芯片组和基板。 相同芯片组中的芯片通过焊盘彼此电连接或与基板电连接。 最后，用模具化合物包封衬底的前表面，支撑构件，芯片组和胶层。 此外，在基板的背面上沉积多个倒装芯片。

公开(公告)号：US06281578B1

公开(公告)日：2001-08-28

申请号：US09638989

申请日：2000-08-15

申请人： Randy H. Y. Lo ,  Chi-Chuan Wu ,  Han-Ping Pu ,  Eric Ko

发明人： Randy H. Y. Lo ,  Chi-Chuan Wu ,  Han-Ping Pu ,  Eric Ko

IPC分类号： H01L2334

CPC分类号： H01L23/49531 ,  H01L23/49575 ,  H01L23/49861 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A multi-chip module (MCM) integrated circuit package structure is proposed, which can be used to pack a plurality of semiconductor chips of different functions while nonetheless allowing the overall package size to be as small as some existing types of integrated circuit packages, such as the SO (Small Outline) and QFP (Quad Flat Package) types, so that it can be manufactured using the existing fabrication equipment. The proposed MCM integrated circuit package structure is characterized in the use of a substrate having a centrally-located opening, and at least one semiconductor chip is mounted on the front surface of the substrate and a semiconductor chip of a central-pad type having a plurality of centrally-located bonding pads is mounted on the back surface of the substrate with the centrally-located bonding pads being exposed through the opening. This arrangement allows the overall package size to be made very compact and also allows the wiring to the central-pad type semiconductor chip to be shortened.

摘要翻译： 提出了一种多芯片模块（MCM）集成电路封装结构，可用于封装多个不同功能的半导体芯片，同时允许整体封装尺寸与现有类型的集成电路封装一样小，如 作为SO（小外形）和QFP（四方扁平封装）类型，因此可以使用现有的制造设备制造。 所提出的MCM集成电路封装结构的特征在于使用具有居中定位的开口的衬底，并且至少一个半导体芯片安装在衬底的前表面上，以及具有多个中心焊盘的半导体芯片 中心定位的焊盘安装在基板的背面，中心位置的焊盘通过开口露出。 这种布置使得整体封装尺寸变得非常紧凑，并且还允许缩短到中心焊盘型半导体芯片的布线。

公开(公告)号：US20070284710A1

公开(公告)日：2007-12-13

申请号：US11891926

申请日：2007-08-14

申请人： Chi-Chuan Wu ,  Chien-Ping Huang ,  Han-Ping Pu

发明人： Chi-Chuan Wu ,  Chien-Ping Huang ,  Han-Ping Pu

IPC分类号： H01L23/495 ,  H01L21/00

CPC分类号： H01L24/16 ,  H01L23/4951 ,  H01L23/49558 ,  H01L23/49575 ,  H01L2224/13099 ,  H01L2224/16245 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00

摘要： A flip-ship semiconductor package with a lead frame as a chip carrier is provided, wherein a plurality of leads of the lead frame are each formed with at least a dam member thereon. When a chip is mounted on the lead frame by means of solder bumps, each of the solder bumps is attached to the corresponding one of the leads at a position between the dam member and an inner end of the lead. During a reflow-soldering process for wetting the solder bumps to the leads, the dam members would help control collapse height of the solder bumps, so as to enhance resistance of the solder bumps to thermal stress generated by CTE (coefficient of thermal expansion) mismatch between the chip and the leads, thereby preventing incomplete electrical connection between the chip and the leads.

摘要翻译： 提供一种具有引线框架作为芯片载体的翻转半导体封装，其中引线框架的多个引线至少形成有至少一个阻挡构件。 当通过焊料凸块将芯片安装在引线框架上时，每个焊料凸块在引线的阻挡件和引线的内端之间的位置附接到相应的一个引线。 在用于将焊料凸点润湿到引线的回流焊接过程中，阻挡构件将有助于控制焊料凸块的塌陷高度，从而增强焊料凸块对CTE产生的热应力的阻力（热膨胀系数）不匹配 在芯片和引线之间，从而防止芯片和引线之间的不完全的电连接。

公开(公告)号：US06781222B2

公开(公告)日：2004-08-24

申请号：US09932053

申请日：2001-08-18

申请人： Chi Chuan Wu ,  Chian Ping Huang ,  Jui-Yu Chuang ,  Ho-Yi Tsai ,  Yude Chu

发明人： Chi Chuan Wu ,  Chian Ping Huang ,  Jui-Yu Chuang ,  Ho-Yi Tsai ,  Yude Chu

IPC分类号： H01L2306

CPC分类号： H01L24/32 ,  H01L23/3128 ,  H01L23/642 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83136 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor package and its fabricating method are proposed, in which a plurality of passive devices are integrated under a semiconductor chip, so as to increase the layout number of the passive devices in the semiconductor package and enhance the flexibility of substrate routability, as well as reduce an occupied area of a substrate for miniaturize the semiconductor package in profile. Moreover, as the integrated passive devices are further encapsulated by using an insulative material prior to a molding process, the dislocation of the passive devices caused by a high temperature and mold flow of a molding resin can be prevented from occurrence during molding. Furthermore, the encapsulated passive devices are prevented from contacting bonding wires, allowing the occurrence of short circuit to be avoided and quality of the packaged product to be assured.

摘要翻译： 提出了一种半导体封装及其制造方法，其中多个无源器件集成在半导体芯片之下，以便增加半导体封装中的无源器件的布局数量并提高衬底可路由性的灵活性，以及 减少基板的占用面积，以使半导体封装的形状小型化。 此外，由于通过在模制工艺之前使用绝缘材料进一步封装集成的无源器件，因此可以防止在模制期间由模制树脂的高温和模具流引起的无源器件的位错。 此外，防止封装的无源器件接触接合线，从而避免短路的发生，并确保封装产品的质量。