公开(公告)号：US06717846B1

公开(公告)日：2004-04-06

申请号：US09696085

申请日：2000-10-26

申请人： Peter W. Lee ,  Hung-Sheng Chen ,  Vei-Han Chan

发明人： Peter W. Lee ,  Hung-Sheng Chen ,  Vei-Han Chan

IPC分类号： G11C1616

CPC分类号： H01L27/11521 ,  G11C16/0425 ,  G11C16/0491 ,  H01L27/115

摘要： In this invention a process for a flash memory cell and an architecture for using the flash memory cell is disclosed to provide a nonvolatile memory having a high storage density. Adjacent columns of cells share the same source and the source line connecting these sources runs vertically in the memory layout, connecting to the sources of adjacent columns memory cells. Bit lines connect to drains of cells in adjacent columns and are laid out vertically, alternating with source lines in an every other column scheme. Wordlines made of a second layer of polysilicon form control gates of the flash memory cells and are continuous over the full width of a memory partition. Programming is done in a vertical page using hot electrons to inject charge onto the floating gates. The cells are crased using Fowler-Nordheim tunneling of electrons from the floating gate to the control gate by way of inter polysilicon oxide formed on the walls of the floating gates.

摘要翻译： 在本发明中，公开了一种用于闪存单元的方法和用于使用闪存单元的架构，以提供具有高存储密度的非易失性存储器。 单元格的相邻列共享相同的源，并且连接这些源的源行在存储器布局中垂直运行，连接到相邻列存储单元的源。 位线连接到相邻列中的单元格的漏极，并且在每个其他列方案中垂直布置，与源极线交替。 由第二层多晶硅制成的字线形成闪存单元的控制栅极，并且在存储器分区的整个宽度上是连续的。 使用热电子在垂直页面中进行编程，以将电荷注入到浮动栅极上。 使用Fowler-Nordheim，通过在浮栅的壁上形成的多晶硅氧化物，利用Fowler-Nordheim将浮动栅极的电子隧穿到控制栅极进行电池堆积。

公开(公告)号：US06563742B1

公开(公告)日：2003-05-13

申请号：US10090356

申请日：2002-03-04

申请人： Peter W. Lee ,  Tam H. Tran

发明人： Peter W. Lee ,  Tam H. Tran

IPC分类号： G11C1600

CPC分类号： G11C16/3409 ,  G11C16/0408 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/344 ,  G11C16/3445

摘要： A multiple time programmable (MTP) memory device is achieved. The device comprises, first, a memory cell array including a means of electrical erasability and electrical programmability. The memory cell array comprises, preferably, a Flash memory cell array. A package has an external pin configuration that conforms to the JEDEC standard for an EPROM device wherein an external, positive programming voltage (VPP) pin is provided. Finally, an external, negative erasing voltage (VNN) pin is provided. The VNN pin is, preferably, multiplexed with the chip enable bar (CEB) pin.

摘要翻译： 实现了多时间可编程（MTP）存储器件。 该装置首先包括一个包括电可擦除性和电可编程性的装置的存储单元阵列。 存储单元阵列优选地包括闪存单元阵列。 封装具有符合EPROM器件的JEDEC标准的外部引脚配置，其中提供外部正的编程电压（VPP）引脚。 最后，提供一个外部负的擦除电压（VNN）引脚。 VNN引脚优选地与芯片使能条（CEB）引脚复用。

公开(公告)号：US06319324B1

公开(公告)日：2001-11-20

申请号：US09662248

申请日：2000-09-14

申请人： Bang C. Nguyen ,  Shankar Vankataranan ,  Ruby Liao ,  Peter W. Lee

发明人： Bang C. Nguyen ,  Shankar Vankataranan ,  Ruby Liao ,  Peter W. Lee

IPC分类号： C23C1600

CPC分类号： H01L21/02271 ,  C23C16/0272 ,  C23C16/402 ,  C23C16/45557 ,  H01L21/02164 ,  H01L21/02304 ,  H01L21/31612

摘要： A method and apparatus for reducing surface sensitivity of a TEOS/O3 SACVD silicon oxide layer, formed over a substrate, that deposits a ramp layer while ramping pressure to a target deposition pressure and deposits an SACVD layer over the ramp layer. In one embodiment, the flow of ozone is stopped during the pressure ramp-up to control the thickness of the ramp layer.

摘要翻译： 一种用于降低在衬底上形成的TEOS / O 3 SACVD氧化硅层的表面灵敏度的方法和装置，其沉积斜坡层，同时将压力升高到目标沉积压力，并在斜坡层上沉积SACVD层。 在一个实施例中，在压力升高期间停止臭氧流以控制斜坡层的厚度。

公开(公告)号：US5958510A

公开(公告)日：1999-09-28

申请号：US583888

申请日：1996-01-08

申请人： Visweswaren Sivaramakrishnam ,  Bang C. Nguyen ,  Gayathri Rao ,  Stuardo Robles ,  Gary L. Fong ,  Vicente Lim ,  Peter W. Lee

发明人： Visweswaren Sivaramakrishnam ,  Bang C. Nguyen ,  Gayathri Rao ,  Stuardo Robles ,  Gary L. Fong ,  Vicente Lim ,  Peter W. Lee

IPC分类号： B05D7/24 ,  C23C16/44 ,  C23C16/452 ,  H01L21/312 ,  C23C16/00

CPC分类号： B05D1/60 ,  C23C16/44 ,  C23C16/452 ,  H01L21/312

摘要： A method and apparatus are disclosed for forming thin polymer layers on semiconductor substrates. In one embodiment, the method and apparatus include the sublimation of stable dimer parylene material, the pyrolytic conversion of such gaseous dimer material into reactive monomers, and for the optional blending of the resulting gaseous parylene monomers with one or more polymerizable materials in gaseous form capable of copolymerizing with the parylene monomers to form a low dielectric constant polymerized parylene material. An apparatus is also disclosed which provides for the distribution of the polymerizable gases into the deposition chamber, for cooling the substrate down to a temperature at which the gases will condense to form a polymerized dielectric material, for heating the walls of the deposition chamber to inhibit formation and accumulation of polymerized residues thereon, and for recapturing unreacted monomeric vapors exiting the deposition chamber. An apparatus is further provided downstream of the deposition chamber to control both the flow rate or residence time of the reactive monomer in the deposition chamber as well as to control the pressure of the deposition chamber. Provision is further made for an electrical bias to permit the apparatus to function as a plasma etch chamber, for in situ plasma cleaning of the chamber between depositions, for enhancing cracking of polymerizable precursor material, for heating the walls of the chamber and for providing heat sufficient to prevent polymerization in the gas phase.

摘要翻译： 公开了用于在半导体衬底上形成薄聚合物层的方法和装置。 在一个实施方案中，该方法和装置包括稳定的二聚聚对二甲苯材料的升华，这种气态二聚体材料的热解转化为反应性单体，以及任选地将得到的气体聚对二甲苯单体与一种或多种气态形式的可聚合材料混合 与聚对二甲苯单体共聚以形成低介电常数的聚对二甲苯聚合物。 还公开了一种设备，其提供可聚合气体分布到沉积室中，用于将衬底冷却至气体冷凝以形成聚合电介质材料的温度，以加热沉积室的壁以抑制 在其上聚合的残余物的形成和积累，以及用于重新捕获离开沉积室的未反应的单体蒸气。 还在沉积室的下游设置一个装置，以控制反应性单体在沉积室中的流速或停留时间以及控制沉积室的压力。 进一步提供电偏压以允许该装置用作等离子体蚀刻室，用于沉积之间的腔室的原位等离子体清洁，用于增强可聚合前体材料的裂化，用于加热室的壁并提供热量 足以防止气相中的聚合。

公开(公告)号：US5354387A

公开(公告)日：1994-10-11

申请号：US935951

申请日：1992-08-25

申请人： Peter W. Lee ,  David N. K. Wang ,  Makoto Nagashima ,  Kazuto Fukuma ,  Tetsuya Sato

发明人： Peter W. Lee ,  David N. K. Wang ,  Makoto Nagashima ,  Kazuto Fukuma ,  Tetsuya Sato

IPC分类号： C23C16/40 ,  H01L21/316 ,  H01L23/29 ,  H01L23/31 ,  H01L23/532 ,  H01L29/12 ,  H01L21/00 ,  H01L21/02 ,  H01L21/302

CPC分类号： H01L21/02129 ,  C23C16/401 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02343 ,  H01L21/31625 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S148/118

摘要： A composite BPSG insulating and planarizing layer is formed over stepped surfaces of a semiconductor wafer by a novel two step process. The composite BPSG layer is characterized by the absence of discernible voids and a surface which is resistant to loss of boron in a subsequent etching step. The two step deposition process comprises a first step to form a void-free BPSG layer by a CVD deposition using gaseous sources of phosphorus and boron dopants and tetraethylorthosilicate (TEOS) as the source of silicon; and then a second step to form a capping layer of BPSG by a plasma-assisted CVD deposition process while again using gaseous sources of phosphorus and boron dopants, and TEOS as the source of silicon, to provide a BPSG cap layer having a surface which is non-hygroscopic and resistant to loss of boron by subsequent etching.

摘要翻译： 通过新的两步法在半导体晶片的台阶表面上形成复合BPSG绝缘和平坦化层。 复合BPSG层的特征在于在随后的蚀刻步骤中不存在可辨别的空隙和耐受硼损失的表面。 两步沉积工艺包括通过使用磷和硼掺杂剂的气态源和原硅酸四乙酯（TEOS）作为硅源的CVD沉积来形成无空隙的BPSG层的第一步骤; 然后第二步骤，通过等离子体辅助CVD沉积工艺形成BPSG的覆盖层，同时再次使用磷和硼掺杂物的气体源和TEOS作为硅源，以提供具有表面的BPSG盖层 通过随后的蚀刻，不吸湿并且耐硼损失。

公开(公告)号：US5166101A

公开(公告)日：1992-11-24

申请号：US649172

申请日：1991-02-01

申请人： Peter W. Lee ,  David N. K. Wang ,  Makoto Nagashima ,  Kazuto Fukuma ,  Tetsuya Sato

发明人： Peter W. Lee ,  David N. K. Wang ,  Makoto Nagashima ,  Kazuto Fukuma ,  Tetsuya Sato

IPC分类号： C23C16/40 ,  H01L21/316 ,  H01L23/29 ,  H01L23/31 ,  H01L23/532

CPC分类号： H01L21/02129 ,  C23C16/401 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02343 ,  H01L21/31625 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S148/118

摘要： A composite BPSG insulating and planarizing layer is formed over stepped surfaces of a semiconductor wafer by a novel two step process. The composite BPSG layer is characterized by the absence of discernible voids and a surface which is resistant to loss of boron in a subsequent etching step. The two step deposition process comprises a first step to form a void-free BPSG layer by a CVD deposition using gaseous sources of phosphorus and boron dopants and tetraethylorthosilicate (TEOS) as the source of silicon; and then a second step to form a capping layer of BPSG by a plasma-assisted CVD deposition process while again using gaseous sources of phosphorus and boron dpoants, and TEOS as the source of silicon, to provide a BPSG cap layer having a surface which is non-hygroscopic and resistant to loss of boron by subsequent etching.

摘要翻译： 通过新的两步法在半导体晶片的台阶表面上形成复合BPSG绝缘和平坦化层。 复合BPSG层的特征在于在随后的蚀刻步骤中不存在可辨别的空隙和耐受硼损失的表面。 两步沉积工艺包括通过使用磷和硼掺杂剂的气态源和原硅酸四乙酯（TEOS）作为硅源的CVD沉积来形成无空隙的BPSG层的第一步骤; 然后第二步骤，通过等离子体辅助CVD沉积工艺形成BPSG的覆盖层，同时再次使用磷和硼的气体源和TEOS作为硅源，以提供具有表面的BPSG盖层 通过随后的蚀刻，不吸湿并且耐硼损失。

公开(公告)号：US4721598A

公开(公告)日：1988-01-26

申请号：US011751

申请日：1987-02-06

申请人： Peter W. Lee

发明人： Peter W. Lee

IPC分类号： B22F7/06 ,  B22F7/00

CPC分类号： B22F7/06 ,  Y10T428/1209 ,  Y10T428/12097

摘要： A powder metal composite made up of first and second powder metal bodies assembled in a mold cavity with the bodies separated by a divider ring and with the bodies being in concentric relationship such that the assembled bodies and divider ring can be simultaneously compacted and subsequently simultaneously sintered to form the desired composite metal article. In practicing the method of forming a composite metal article one of the bodies may be selected from a base powder metal and the other body may be selected from a high performance alloy powder metal, and the divider ring may be selected from a low melting point metal such as copper that will dissolve itself into the powders during sintering and enhance mechanical properties of the sintered compact article. The composital metal article may be used as it is if the density for its intended uses is satisfactory, or such article may be further densified by being subjected to an additional hot forging operation with the article sintered thereafter if deemed necessary.

公开(公告)号：US07087953B2

公开(公告)日：2006-08-08

申请号：US11040862

申请日：2005-01-21

申请人： Peter W. Lee

发明人： Peter W. Lee

IPC分类号： H01L29/788

CPC分类号： H01L27/105 ,  G11C16/0408 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

摘要： A method for making a unified non-volatile memory (NVM) comprised of a NOR-type flash memory, a NAND-type flash memory, and a 3-transistor EEPROM integrated on the same chip is achieved. This unified NVM can be used in advanced smart card applications. The unification is achieved by forming the array of NVM cells and their peripheral high-voltage NMOS-FETs in a deep triple-P well or P-substrate while making high-voltage PMOS-FETs in a deep N well with breakdown voltages greater than +18 V and greater than −18 V, respectively. This novel NVM structure allows one to have compatible breakdown voltages for programming/erasing (charging and discharging) the floating-gate transistors in the NOR flash, the NAND flash, and 3-transistor EEPROM memory.

摘要翻译： 实现了一种用于制造集成在同一芯片上的NOR型闪速存储器，NAND型闪速存储器和3晶体管EEPROM组成的统一的非易失性存储器（NVM）的方法。 这种统一的NVM可用于高级智能卡应用。 通过在深三阱阱或P衬底中形成NVM单元阵列及其外围高压NMOS-FET，同时在深N阱中制造高电压PMOS-FET，击穿电压大于+ 18 V，大于-18 V。 这种新颖的NVM结构允许具有用于在NOR闪存，NAND闪存和3晶体管EEPROM存储器中的浮动栅极晶体管的编程/擦除（充电和放电）的兼容击穿电压。

公开(公告)号：US06258668B1

公开(公告)日：2001-07-10

申请号：US09487501

申请日：2000-01-19

申请人： Peter W. Lee ,  Hung-Sheng Chen ,  Vei-Han Chan

发明人： Peter W. Lee ,  Hung-Sheng Chen ,  Vei-Han Chan

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  G11C16/0425 ,  G11C16/0491 ,  H01L27/115

摘要： In this invention a process for a flash memory cell and an architecture for using the flash memory cell is disclosed to provide a nonvolatile memory having a high storage density. Adjacent columns of cells share the same source and the source line connecting these sources runs vertically in the memory layout, connecting to the sources of adjacent columns memory cells. Bit lines connect to drains of cells in adjacent columns and are laid out vertically, alternating with source lines in an every other column scheme. Wordlines made of a second layer of polysilicon form control gates of the flash memory cells and are continuous over the full width of a memory partition. Programming is done in a vertical page using hot electrons to inject charge onto the floating gates. the cells are erased using Fowler-Nordheim tunneling of electrons from the floating gate to the control gate by way of inter polysilicon oxide formed on the walls of the floating gates.

摘要翻译： 在本发明中，公开了一种用于闪存单元的方法和用于使用闪存单元的架构，以提供具有高存储密度的非易失性存储器。 单元格的相邻列共享相同的源，并且连接这些源的源行在存储器布局中垂直运行，连接到相邻列存储单元的源。 位线连接到相邻列中的单元格的漏极，并且在每个其他列方案中垂直布置，与源极线交替。 由第二层多晶硅制成的字线形成闪存单元的控制栅极，并且在存储器分区的整个宽度上是连续的。 使用热电子在垂直页面中进行编程，以将电荷注入到浮动栅极上。 通过使用Fowler-Nordheim从浮置栅极到控制栅极的隧道，通过在浮栅的壁上形成的多晶硅氧化物来消除电池。

公开(公告)号：US6149974A

公开(公告)日：2000-11-21

申请号：US851830

申请日：1997-05-05

申请人： Bang C. Nguyen ,  Shankar Vankataranan ,  Ruby Liao ,  Peter W. Lee

发明人： Bang C. Nguyen ,  Shankar Vankataranan ,  Ruby Liao ,  Peter W. Lee

IPC分类号： H01L21/31 ,  C23C16/02 ,  C23C16/40 ,  C23C16/44 ,  C23C16/455 ,  H01L21/316

CPC分类号： H01L21/02271 ,  C23C16/0272 ,  C23C16/402 ,  C23C16/45557 ,  H01L21/02164 ,  H01L21/02304 ,  H01L21/31612

摘要： A method and apparatus for reducing surface sensitivity of a TEOS/O.sub.3 SACVD silicon oxide layer, formed over a substrate, that deposits a ramp layer while ramping pressure to a target deposition pressure and deposits an SACVD layer over the ramp layer. In one embodiment, the flow of ozone is stopped during the pressure ramp-up to control the thickness of the ramp layer.

摘要翻译： 一种用于降低在衬底上形成的TEOS / O 3 SACVD氧化硅层的表面灵敏度的方法和装置，其沉积斜坡层，同时将压力升高到目标沉积压力，并在斜坡层上沉积SACVD层。 在一个实施例中，在压力升高期间停止臭氧流以控制斜坡层的厚度。