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公开(公告)号：US20240111457A1
公开(公告)日：2024-04-04
申请号：US18496887
申请日：2023-10-29
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Scott C. Best
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0629 , G06F3/0673 , G06F13/1673 , G11C5/04 , Y02D10/00
Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. The memory module additionally includes a command input port to receive command and address signals from a controller and, also in support of capacity extensions, a command relay circuit coupled to the command port to convey the commands and addresses from the memory module to another module or modules. Relaying commands and addresses introduces a delay, and the buffer system that manages communication between the memory controller and the memory devices can be configured to time data communication to account for that delay.
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公开(公告)号：US11942182B2
公开(公告)日：2024-03-26
申请号：US18089668
申请日：2022-12-28
Applicant: Rambus Inc.
Inventor： Scott C. Best , Frederick A. Ware , William N. Ng
CPC classification number: G11C7/1093 , G11C5/04 , G11C7/1003 , G11C7/1066
Abstract: A memory module can be programmed to deliver relatively wide, low-latency data in a first access mode, or to sacrifice some latency in return for a narrower data width, a narrower command width, or both, in a second access mode. The narrow, higher-latency mode requires fewer connections and traces. A controller can therefore support more modules, and thus increased system capacity. Programmable modules thus allow computer manufacturers to strike a desired balance between memory latency, capacity, and cost.
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公开(公告)号：US20240079079A1
公开(公告)日：2024-03-07
申请号：US18233257
申请日：2023-08-11
Applicant: Rambus Inc.
Inventor： Scott C. Best , John Eric Linstadt , Paul William Roukema
CPC classification number: G11C29/4401 , G11C5/04 , G11C11/401 , G11C29/022 , G11C29/52 , G11C29/76 , G11C29/783 , G11C29/88 , G11C2029/4402
Abstract: A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.
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公开(公告)号：US11782807B2
公开(公告)日：2023-10-10
申请号：US17744347
申请日：2022-05-13
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Brent S. Haukness , John Eric Linstadt , Scott C. Best
IPC: G06F11/20 , G11C11/4093 , G11C29/52
CPC classification number: G06F11/2094 , G11C11/4093 , G11C29/52 , G06F2201/82
Abstract: A memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.
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公开(公告)号：US11669124B2
公开(公告)日：2023-06-06
申请号：US17715869
申请日：2022-04-07
Applicant: Rambus Inc.
Inventor： Scott C. Best , Abhijit M. Abhyankar , Kun-Yung Chang , Frank Lambrecht
CPC classification number: G06F1/08 , G06F1/12 , G11C29/02 , G11C29/022 , G11C29/028 , G11C29/50012 , H04L7/0008 , H04L7/0033 , H04L7/0091 , H04L7/033 , H04L7/10 , H04L25/14 , H04L7/0004
Abstract: A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.
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Patent Agency Ranking
公开(公告)号：US20230170039A1
公开(公告)日：2023-06-01
申请号：US18074188
申请日：2022-12-02
Applicant: Rambus Inc.
Inventor： Scott C. Best , John Eric Linstadt , Paul William Roukema
CPC classification number: G11C29/4401 , G11C29/88 , G11C5/04 , G11C11/401 , G11C29/022 , G11C29/76 , G11C29/783 , G11C29/52 , G11C2029/4402
Abstract: A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.
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公开(公告)号：US11573849B2
公开(公告)日：2023-02-07
申请号：US17236445
申请日：2021-04-21
Applicant: Rambus Inc.
Inventor： Thomas J. Giovannini , Catherine Chen , Scott C. Best , John Eric Linstadt , Frederick A. Ware
Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.
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公开(公告)号：US11567695B2
公开(公告)日：2023-01-31
申请号：US17575524
申请日：2022-01-13
Applicant: Rambus Inc.
Inventor： Scott C. Best
Abstract: A buffer circuit includes a primary interface, a secondary interface, and an encoder/decoder circuit. The primary interface is configured to communicate on an n-bit channel, wherein n parallel bits on the n-bit channel are coded using data bit inversion (DBI). The secondary interface is configured to communicate with a plurality of integrated circuit devices on a plurality of m-bit channels, each m-bit channel transmitting m parallel bits without using DBI. And the encoder/decoder circuit is configured to translate data words between the n-bit channel of the primary interface and the plurality of m-bit channels of the secondary interface.
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公开(公告)号：US20220206708A1
公开(公告)日：2022-06-30
申请号：US17575524
申请日：2022-01-13
Applicant: Rambus Inc.
Inventor： Scott C. Best
Abstract: A buffer circuit includes a primary interface, a secondary interface, and an encoder/decoder circuit. The primary interface is configured to communicate on an n-bit channel, wherein n parallel bits on the n-bit channel are coded using data bit inversion (DBI). The secondary interface is configured to communicate with a plurality of integrated circuit devices on a plurality of m-bit channels, each m-bit channel transmitting m parallel bits without using DBI. And the encoder/decoder circuit is configured to translate data words between the n-bit channel of the primary interface and the plurality of m-bit channels of the secondary interface.
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公开(公告)号：US20220139446A1
公开(公告)日：2022-05-05
申请号：US17540950
申请日：2021-12-02
Applicant: Rambus Inc.
Inventor： Scott C. Best , Ming Li
IPC: G11C11/4093 , H01L25/10 , G11C5/02 , H01L25/18 , H01L25/065 , G11C11/4096 , G11C5/04 , H01L23/48 , G11C11/406 , H01L23/00
Abstract: A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.
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