公开(公告)号：US10318434B2

公开(公告)日：2019-06-11

申请号：US15905746

申请日：2018-02-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Frederic Sala ,  Chaohong Hu ,  Hongzhong Zheng ,  Dimin Niu ,  Mu-Tien Chang

IPC: G06F12/10 ,  G06F12/1018 ,  G06F12/0802 ,  G11C29/00 ,  G06F3/06

Abstract: A method of memory deduplication includes identifying hash tables each corresponding to a hash function, and each including physical buckets, each physical bucket including ways and being configured to store data, identifying virtual buckets each including some physical buckets, and each sharing a physical bucket with another virtual bucket, identifying each of the physical buckets having data stored thereon as being assigned to a single virtual bucket, hashing a data line according to a hash function to produce a hash value, determining whether a corresponding virtual bucket has available space for a block of data according to the hash value, sequentially moving data from the corresponding virtual bucket to an adjacent virtual bucket when the corresponding virtual bucket does not have available space until the corresponding virtual bucket has space for the block of data, and storing the block of data in the corresponding virtual bucket.

公开(公告)号：US10268541B2

公开(公告)日：2019-04-23

申请号：US15286460

申请日：2016-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng ,  Hyun-Joong Kim ,  Won-hyung Song ,  Jangseok Choi

IPC: G06F11/00 ,  G06F11/10 ,  G11C29/52 ,  G11C5/04 ,  G11C29/42

Abstract: A method of correcting a memory error of a dynamic random-access memory module (DRAM) using a double data rate (DDR) interface, the method includes conducting a memory transaction including multiple bursts with a memory controller to send data from data chips of the DRAM to the memory controller, detecting one or more errors using an ECC chip of the DRAM, determining a number of the bursts having the errors using the ECC chip of the DRAM, determining whether the number of the bursts having the errors is greater than a threshold number, determining a type of the errors, and directing the memory controller based on the determined type of the errors, wherein the DRAM includes a single ECC chip per memory channel.

公开(公告)号：US09846650B2

公开(公告)日：2017-12-19

申请号：US14732654

申请日：2015-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng

IPC: G06F12/08 ,  G06F12/0877 ,  G06F3/06

CPC classification number: G06F12/0877 ,  G06F3/0611 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F13/16 ,  G06F2212/60 ,  G06F2212/7203

Abstract: A Solid State Drive (SSD) is disclosed. The SSD can include a host interface logic, a data input buffer, a data output buffer, and a buffer manager to manage the data input buffer and data output buffer. A re-order logic can advise the buffer manager about which data should be returned to the host computer from the data output buffer.

公开(公告)号：US09830086B2

公开(公告)日：2017-11-28

申请号：US15174761

申请日：2016-06-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng ,  Sun Young Lim ,  Indong Kim

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0632 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/068 ,  G06F3/0685

Abstract: A hybrid memory controller performs receiving first and second central processing unit (CPU) requests to write to/read from a hybrid memory group, identifying a volatile memory device and a non-volatile memory device as a first target and second target of the first and second CPU requests, respectively, by decoding and address mapping of the first and second CPU requests, queuing the first and second CPU requests in first and second buffers, respectively, generating, based on an arbitration policy, a first command corresponding to one of the first and second CPU requests to an associated one of the first and second targets, and generating a second command corresponding to another one of the first and second CPU requests to an associated another one of the first and second targets, and transmitting the first and second commands to respective ones of the volatile and non-volatile memory devices.

公开(公告)号：US09785570B2

公开(公告)日：2017-10-10

申请号：US14863446

申请日：2015-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chaohong Hu ,  Hongzhong Zheng ,  Dimin Niu

IPC: G06F11/10 ,  G06F12/1009

CPC classification number: G06F12/1009 ,  G06F11/1048 ,  G06F12/0246 ,  G06F12/0607 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/65 ,  G06F2212/7201

Abstract: An embodiment includes a system, comprising: an Error Correcting Code (ECC) memory comprising a plurality of memory locations, each memory location corresponding to a device address of the ECC memory; a system management bus (SMB); a baseboard management controller (BMC) coupled to the ECC memory through the SMB; and an operating system comprising a driver module coupled to the BMC through the SMB, the driver module being configured to receive through the Memory device address information associated with the ECC memory and to convert the device address information into physical address information independent of an ECC memory controller.

公开(公告)号：US20170286003A1

公开(公告)日：2017-10-05

申请号：US15161136

申请日：2016-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Frederic Sala ,  Chaohong Hu ,  Hongzhong Zheng ,  Dimin Niu ,  Mu-Tien Chang

IPC: G06F3/06 ,  G06F12/10

CPC classification number: G06F12/1018 ,  G06F3/0619 ,  G06F3/0641 ,  G06F3/065 ,  G06F3/0685 ,  G06F12/0802 ,  G11C29/74

Abstract: A method of memory deduplication includes identifying hash tables each corresponding to a hash function, and each including physical buckets, each physical bucket including ways and being configured to store data, identifying virtual buckets each including some physical buckets, and each sharing a physical bucket with another virtual bucket, identifying each of the physical buckets having data stored thereon as being assigned to a single virtual bucket, hashing a data line according to a hash function to produce a hash value, determining whether a corresponding virtual bucket has available space for a block of data according to the hash value, sequentially moving data from the corresponding virtual bucket to an adjacent virtual bucket when the corresponding virtual bucket does not have available space until the corresponding virtual bucket has space for the block of data, and storing the block of data in the corresponding virtual bucket.

公开(公告)号：US09524769B2

公开(公告)日：2016-12-20

申请号：US14850938

申请日：2015-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Krishna Malladi ,  Dimin Niu ,  Hongzhong Zheng

IPC: G11C5/14 ,  G11C11/406 ,  G11C11/4076

CPC classification number: G11C11/40615 ,  G11C5/04 ,  G11C5/14 ,  G11C11/40618 ,  G11C11/4076

Abstract: A dynamic Random Access Memory (DRAM) module (105) is disclosed. The DRAM module (105) can includes a plurality of banks (205-1, 205-2, 205-3, 205-4) to store data and a refresh engine (115) that can be used to refresh one of the plurality of banks (205-1, 205-2, 205-3, 205-4). The DRAM module (105) can also include a Smart Refresh Component (305) that can advise the refresh engine (115) which bank to refresh using an out-of-order per-bank refresh. The Smart Refresh Component (305) can use a logic (415) to identify a farthest bank in the pending transactions in the transaction queue (430) at the time of refresh.

Abstract translation: 公开了一种动态随机存取存储器（DRAM）模块（105）。 DRAM模块（105）可以包括用于存储数据的多个存储体（205-1,205-2,205-3,205-4）和可用于刷新多个存储数据中的一个的刷新引擎（115） 银行（205-1,205-2,205-3,205-4）。 DRAM模块（105）还可以包括智能刷新组件（305），该智能刷新组件可以通过使用每次刷新无序刷新哪个存储体来刷新刷新引擎（115）。 在刷新时，智能刷新组件（305）可以使用逻辑（415）来识别事务队列（430）中的待处理事务中的最远存储体。

公开(公告)号：US12248402B2

公开(公告)日：2025-03-11

申请号：US18070328

申请日：2022-11-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. Malladi ,  Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng

IPC: G06F12/0879 ,  G11C11/417

Abstract: A high bandwidth memory system. In some embodiments, the system includes: a memory stack having a plurality of memory dies and eight 128-bit channels; and a logic die, the memory dies being stacked on, and connected to, the logic die; wherein the logic die may be configured to operate a first channel of the 128-bit channels in: a first mode, in which a first 64 bits operate in pseudo-channel mode, and a second 64 bits operate as two 32-bit fine-grain channels, or a second mode, in which the first 64 bits operate as two 32-bit fine-grain channels, and the second 64 bits operate as two 32-bit fine-grain channels.

公开(公告)号：US12197726B2

公开(公告)日：2025-01-14

申请号：US18369079

申请日：2023-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Prasun Gera ,  Dimin Niu ,  Hongzhong Zheng

IPC: G06F3/06 ,  G06F9/30 ,  G06F15/78

Abstract: A 3D-stacked memory device including: a base die including a plurality of switches to direct data flow and a plurality of arithmetic logic units (ALUs) to compute data; a plurality of memory dies stacked on the base die; and an interface to transfer signals to control the base die.

公开(公告)号：US12189546B2

公开(公告)日：2025-01-07

申请号：US17872987

申请日：2022-07-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng ,  Sun Young Lim ,  Indong Kim ,  Jangseok Choi ,  Craig Hanson

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

Abstract: A memory module that includes a non-volatile memory and an asynchronous memory interface to interface with a memory controller is presented. The asynchronous memory interface may use repurposed pins of a double data rate (DDR) memory channel to send an asynchronous data to the memory controller. The asynchronous data may be device feedback indicating a status of the non-volatile memory.