公开(公告)号：US20170373079A1

公开(公告)日：2017-12-28

申请号：US15483862

申请日：2017-04-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Fumitaka AMANO ,  Raghuveer S. MAKALA ,  Fei ZHOU ,  Keerti SHUKLA

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L21/768 ,  H01L23/532 ,  H01L27/11582 ,  H01L27/1157

CPC classification number: H01L27/11556 ,  H01L21/28282 ,  H01L21/76847 ,  H01L23/53266 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7926

Abstract: Memory stack structures are formed through an alternating stack of insulating layers and sacrificial material layers. Backside recesses are formed by removal of the sacrificial material layers selective to the insulating layers and the memory stack structures. A barrier layer stack including a crystalline electrically conductive barrier layer and an amorphous barrier layer is formed in the backside recesses prior to formation of a metal fill material layer.

公开(公告)号：US20230402387A1

公开(公告)日：2023-12-14

申请号：US17806415

申请日：2022-06-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Ryo KAMBAYASHI ,  Fumitaka AMANO

IPC: H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/535 ,  H01L23/5283 ,  H01L23/53266 ,  H01L27/11556 ,  H01L27/11582

Abstract: A three dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate; memory stack structures vertically extending through the alternating stack; and a backside trench fill structure. The backside trench fill structure includes a backside trench insulating spacer and a backside contact via structure. The backside contact via structure may include a tapered metallic nitride liner and at least one core fill conductive material portion. Alternatively, the backside contact via structure may include a tungsten nitride liner, a metallic nitride liner other than tungsten nitride, and at least one core fill conductive material portion.

公开(公告)号：US20230369208A1

公开(公告)日：2023-11-16

申请号：US17662926

申请日：2022-05-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Fei ZHOU

IPC: H01L23/528 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/5283 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings and including a respective vertical semiconductor channel and a respective vertical stack of memory elements, and a first backside trench fill structure and a second backside trench fill structure. Each of the electrically conductive layers includes a respective metal nitride liner and a respective metal fill material region. The respective metal fill material region includes a respective first-thickness portion having a respective first vertical thickness and a respective second-thickness portion having a respective second vertical thickness that is greater than the respective first vertical thickness.

公开(公告)号：US20230269939A1

公开(公告)日：2023-08-24

申请号：US17679335

申请日：2022-02-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely SAID ,  Senaka KANAKAMEDALA ,  Raghuveer S. MAKALA ,  Peng ZHANG ,  Yanli ZHANG

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening fill structure including a vertical semiconductor channel and a memory film. The memory film includes a tunneling dielectric layer in contact with the vertical semiconductor channel, a first vertical stack of first dielectric oxide material portions located at levels of the insulating layers and including a dielectric oxide material of a first element, and a second vertical stack of second dielectric oxide material portions located at levels of the electrically conductive layers and including a mixed dielectric oxide material that is a dielectric oxide material of the first element and a second element.

公开(公告)号：US20230223248A1

公开(公告)日：2023-07-13

申请号：US17573452

申请日：2022-01-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fei ZHOU ,  Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Yujin TERASAWA ,  Naoki TAKEGUCHI ,  Kensuke YAMAGUCHI ,  Masaaki HIGASHITANI

IPC: H01L21/02 ,  C23C16/458

CPC classification number: H01L21/02175 ,  H01L21/02271 ,  C23C16/4583

Abstract: A method of depositing a metal includes providing a structure a process chamber, and providing a metal fluoride gas and a growth-suppressant gas into the process chamber to deposit the metal over the structure. The metal may comprise a word line or another conductor of a three-dimensional memory device.

公开(公告)号：US20230157013A1

公开(公告)日：2023-05-18

申请号：US17525233

申请日：2021-11-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Fei ZHOU

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L21/768

CPC classification number: H01L27/11556 ,  H01L21/76802 ,  H01L21/76829 ,  H01L27/11582

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, etch stop plates located in the staircase region, laterally and vertically spaced apart among one another, and overlying an end portion of a respective one of the electrically conductive layers, and contact via structures located in a staircase region, vertically extending through a respective one of the etch stop plates, and contacting a respective one of the electrically conductive layers.

公开(公告)号：US20230090951A1

公开(公告)日：2023-03-23

申请号：US17479637

申请日：2021-09-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Rahul SHARANGPANI ,  Fei ZHOU

IPC: H01L23/522 ,  H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor structure includes semiconductor devices located over a substrate, bit lines electrically connected to the semiconductor devices and having a respective reentrant vertical cross-sectional profile within a vertical plane that is perpendicular to a lengthwise direction along which the bit lines laterally extend, and dielectric portions that are interlaced with the bit lines along a horizontal direction that is perpendicular to the lengthwise direction. The dielectric portions may contain air gaps. A bit-line-contact via structure can be formed on top of a bit line. In some embodiments, dielectric cap strips may be located on top surface of the dielectric portions and may cover peripheral regions of the top surfaces of the bit lines without covering middle regions of the top surfaces of the bit lines.

公开(公告)号：US20220352193A1

公开(公告)日：2022-11-03

申请号：US17244186

申请日：2021-04-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely SAID ,  Raghuveer S. MAKALA ,  Senaka KANAKAMEDALA ,  Rahul SHARANGPANI

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings extending through the alternating stack, and memory opening fill structures located in the memory openings and containing a respective vertical semiconductor channel and a respective memory film. Each of the electrically conductive layers includes a tubular metallic liner in contact with a respective outer sidewall segment of a respective one of the memory opening fill structures, an electrically conductive barrier layer contacting the respective tubular metallic liner and two of the insulating layers, and a metallic fill material layer contacting the electrically conductive barrier layer, and not contacting the tubular metallic liner or any of the insulating layers. The memory opening fill structures are formed after performing a halogen outgassing anneal through the memory openings to reduce or eliminate the halogen outgassing damage in the layers of the memory film.

公开(公告)号：US20220278216A1

公开(公告)日：2022-09-01

申请号：US17189153

申请日：2021-03-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Xue Bai PITNER ,  Raghuveer S. MAKALA ,  Fei ZHOU ,  Senaka KANAKAMEDALA ,  Ramy Nashed Bassely SAID

IPC: H01L29/423 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11597 ,  H01L29/78 ,  H01L21/28

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and memory opening fill structures located in the memory opening and including a vertical semiconductor channel, a dielectric material liner laterally surrounding the vertical semiconductor channel, and a vertical stack of discrete memory elements laterally surrounding the dielectric material liner. A subset of the insulating layers a lower insulating sublayer, an upper insulating sublayer overlying the lower insulating sublayer, and a center insulating sublayer located between and in contact with the lower insulating sublayer and the upper insulating sublayer.

公开(公告)号：US20220246517A1

公开(公告)日：2022-08-04

申请号：US17166393

申请日：2021-02-03

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Monica TITUS ,  Ramy Nashed Bassely SAID ,  Rahul SHARANGPANI ,  Senaka KANAKAMEDALA ,  Raghuveer S. MAKALA

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/768

Abstract: A semiconductor structure includes at least one first semiconductor device located on a substrate, lower-level dielectric material layers embedding lower-level metal interconnect structures, at least one second semiconductor device and a dielectric material portion that overlie the lower-level dielectric material layers, at least one upper-level dielectric material layer, and an interconnection via structure vertically extending from the at least one upper-level dielectric material layer to a conductive structure that can be a node of the at least one first semiconductor device or one of lower-level metal interconnect structures. The interconnection via structure includes a transition metal layer and a fluorine-doped filler material portion in contact with the transition metal layer, composed primarily of a filler material selected from a silicide of the transition metal element or aluminum oxide, and including fluorine atoms.