公开(公告)号：US5436913A

公开(公告)日：1995-07-25

申请号：US069911

申请日：1993-06-01

申请人： Toshio Yamamura ,  Hiroto Nakai ,  Hideo Kato ,  Kaoru Tokushige ,  Masamichi Asano

发明人： Toshio Yamamura ,  Hiroto Nakai ,  Hideo Kato ,  Kaoru Tokushige ,  Masamichi Asano

IPC分类号： G11C16/34 ,  G06F11/00

CPC分类号： G11C16/3459 ,  G11C16/3454

摘要： A non-volatile semiconductor memory device has writing part (203, 205, 209) for writing data in a non-volatile memory cell in response to a write pulse, readout part (419) for reading out data stored in the memory cell, and verification part (207, 210; 417) for verifying to ensure that normal writing has been completed by reading data from the memory cell after each writing. The device repeats writings unless a normal writing can be confirmed by the verification part. At this time, the writing part can vary writing time and in a part of a sequence of repeating writing unless a normal writing can be confirmed, it sets writing time longer for the next writing action than that for one writing action. Since this setting is performed according to constant multiplication, constant increment, or constant multiplication of accumulated value, necessary time for obtaining normal data write can be reduced.

摘要翻译： 非挥发性半导体存储器件具有写入部分（203,205,209），用于响应写入脉冲在非易失性存储单元中写入数据，用于读出存储在存储器单元中的数据的读出部分（419）以及 验证部件（207,210; 417），用于通过在每次写入之后从存储器单元读取数据来验证以确保正常写入已经完成。 设备重复写入，除非验证部分可以确认正常写入。 此时，写入部分可以改变写入时间，并且在重复写入序列的一部分中，除非正常写入可以被确认，否则为下一个写入动作设置比一个写入动作的写入时间更长的时间。 由于根据常数乘法，常数增量或累积值的常数乘法执行该设置，因此可以减少获得正常数据写入所需的时间。

公开(公告)号：US5428569A

公开(公告)日：1995-06-27

申请号：US38985

申请日：1993-03-29

申请人： Hideo Kato ,  Hiroto Nakai ,  Masamichi Asano ,  Kaoru Tokushige

发明人： Hideo Kato ,  Hiroto Nakai ,  Masamichi Asano ,  Kaoru Tokushige

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/12 ,  G11C16/16 ,  G11C29/00 ,  G11C29/12 ,  G11C29/24 ,  G11C29/50 ,  G11C29/52 ,  G11C7/00

CPC分类号： G11C16/12 ,  G11C16/16 ,  G11C29/50 ,  G11C29/52 ,  G11C16/04

摘要： A non-volatile semiconductor memory device comprises: a plurality of memory cells for electrically rewriting data; a programming and erasing section for executing data writing programs and data erasing operation for the memory cells; a verifying section for discriminating whether a data is written in or erased from one of the memory cells properly whenever data are written to or erased from the memory cells; and an automatic control section for enabling the programming and erasing section to execute the data writing program and erasing operation again whenever the verifying section discriminates that data is not properly written to or erased from one of the memory cells, the data writing program or erasing operation being executed repeatedly by the number of times less than a user-defined maximum program execution or erasing operation number applied externally from the outside of the memory device. Further, the number of data writing and erasing operations can be outputted to the outside of the chip. Therefore, it is possible to optimize the limit of the data writing operation according to the chip samples and to detect the deterioration status of he chip externally from the chip. The reliability of a system using the memory devices can be improved, and further the chip exchange timing can be indicated to the user.

摘要翻译： 非挥发性半导体存储器件包括：用于电重写数据的多个存储单元; 用于对存储单元执行数据写入程序和数据擦除操作的编程和擦除部分; 一个验证部分，用于鉴别每当数据被从存储器单元写入或擦除时，正确地从一个存储器单元写入数据或从其中擦除数据; 以及自动控制部分，用于使编程和擦除部分能够每当验证部分识别数据未被正确地从存储器单元之一写入或擦除时执行数据写入程序和擦除操作，数据写入程序或擦除操作 重复执行小于从存储装置的外部外部施加的用户定义的最大程序执行或擦除操作数的次数。 此外，可以将数据写入和擦除操作的数量输出到芯片的外部。 因此，可以根据芯片样本优化数据写入操作的限制，并且从芯片外部检测芯片的劣化状态。 可以提高使用存储器件的系统的可靠性，并且可以向用户指示芯片交换定时。

公开(公告)号：US5297029A

公开(公告)日：1994-03-22

申请号：US993109

申请日：1992-12-18

申请人： Hiroto Nakai ,  Hideo Kato ,  Kaoru Tokushige ,  Masamichi Asano

发明人： Hiroto Nakai ,  Hideo Kato ,  Kaoru Tokushige ,  Masamichi Asano

IPC分类号： G06F3/06 ,  G11C7/10 ,  G11C8/04 ,  G11C16/04 ,  G11C8/00

CPC分类号： G06F3/0601 ,  G11C16/0483 ,  G11C7/103 ,  G11C8/04 ,  G06F2003/0694

摘要： In reading data, data is transferred to data registers starting from a data read start address to the last address at a row (page), and data at the next page is transferred to the data registers starting from a start address to the last address at that page. These operations are repeated. In writing data from an intermediate address of a page, predetermined data is written in data registers not having write data. It is possible to read data at consecutive pages from a first predetermined column address to the page last address, and to read data at consecutive pages from a second predetermined column address to the page last address. For the data structure having a first data structure and a second data structure, it is possible to continuously read a set of data having both the first and second data structures and a set of data having only the second data structure, improving the efficiency of a system using a semiconductor memory device.

摘要翻译： 在读取数据时，将数据从数据读取开始地址开始传输到一行（页面）的最后一个地址，将数据从数据寄存器传送到数据寄存器，从起始地址开始到最后一个地址 那个页面。 重复这些操作。 在从页面的中间地址写入数据时，将预定数据写入不具有写入数据的数据寄存器中。 可以在从第一预定列地址到页面最后地址的连续页面读取数据，并且从连续页面将数据从第二预定列地址读取到页面最后地址。 对于具有第一数据结构和第二数据结构的数据结构，可以连续读取具有第一和第二数据结构的数据集合和仅具有第二数据结构的一组数据，从而提高 系统使用半导体存储器件。

公开(公告)号：US5257230A

公开(公告)日：1993-10-26

申请号：US565820

申请日：1990-08-13

申请人： Kazuhiko Nobori ,  Taira Iwase ,  Masamichi Asano ,  Makoto Takizawa ,  Shigefumi Ishiguro ,  Kazuo Yonehara ,  Satoshi Nikawa ,  Koji Saito

发明人： Kazuhiko Nobori ,  Taira Iwase ,  Masamichi Asano ,  Makoto Takizawa ,  Shigefumi Ishiguro ,  Kazuo Yonehara ,  Satoshi Nikawa ,  Koji Saito

IPC分类号： H01L21/82 ,  G11C29/00 ,  H01L21/8246 ,  H01L23/525 ,  H01L27/10 ,  G11C17/16

CPC分类号： G11C29/785 ,  H01L23/5256 ,  H01L27/1126 ,  H01L2924/0002

摘要： There is disclosed an improved semiconductor memory device having a regular memory cell array and a spare memory cell array. Each spare memory cell constituting the spare memory cell array includes a first transistor selected by a read word line, whose drain is connected to a spare bit line and source is connected via a fuse to a power supply, and a second transistor connected between the interconnection between the first transistor and fuse and a ground. The fuse is selectively blown by flowing a blowing current through the fuse by selecting the second transistor through a write line to thereby disconnect a discharge current path of the spare bit line. The threshold voltage of the second transistor of the spare memory cell which is made conductive upon selection by the write line when the blowing current flows through the fuse is higher than a potential difference between a potential generated at the write line connected with another spare memory cell and a ground potential. Such a high threshold voltage is obtained by including in manufacture of the memory cell the steps of implanting impurity ions of a first conductivity type to the channel area of a region on the surface of a semiconductor substrate where transistors including the second transistor of a second conductivity type different from the first conductivity type are formed; and implanting impurity ions of the one conductivity type to the channel area of the second transistor and to the channel area of transistors of a conductivity type different from the second transistor; whereby the impurity ions are implanted twice to the channel area of the second transistor.

公开(公告)号：US5138579A

公开(公告)日：1992-08-11

申请号：US632613

申请日：1990-12-26

申请人： Yuuichi Tatsumi ,  Hidenobu Minagawa ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Mizuho Imai

发明人： Yuuichi Tatsumi ,  Hidenobu Minagawa ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Mizuho Imai

IPC分类号： G11C7/00 ,  G11C16/06 ,  G11C16/28 ,  G11C17/00

CPC分类号： G11C16/28

摘要： A semiconductor memory device includes word lines selectively driven by a signal from a row decoder, memory cells connected to word lines, first and second data lines, a bit line connected to receive data from the memory cell and to supply received data to the first data lines, dummy cells connected to word lines, first and second dummy data lines, a dummy bit lines connected to receive data from the dummy memory cell and to supply received data to the first dummy data line, a data sensing circuit for generating an output signal corresponding to a potential difference between the second data line and second dummy data line, a first MOS transistor connected between the first and second data lines, a first load circuit for charging the second data line, a second MOS transistor connected between the first and second dummy data lines, and a second load circuit for charging the second dummy data lines. The memory device further includes a first equalizer circuit connected between the second data line and dummy data line and equalizing potentials at both ends during a predetermined period of time after the semiconductor memory device is set in the active mode, and a second equalizer circuit connected between the data line and dummy data line and equalizing potential as at both ends during a predetermined period of time after the memory device is set in the active mode.

摘要翻译： 半导体存储器件包括由来自行解码器的信号选择性地驱动的字线，连接到字线的存储器单元，第一和第二数据线，连接到从存储器单元接收数据并将接收到的数据提供给第一数据的位线 连接到字线的虚拟单元，第一和第二虚拟数据线，连接成从虚拟存储单元接收数据并将接收到的数据提供给第一虚拟数据线的虚拟位线;数据感测电路，用于产生输出信号 对应于第二数据线和第二虚拟数据线之间的电位差，连接在第一和第二数据线之间的第一MOS晶体管，用于对第二数据线充电的第一负载电路，连接在第一和第二数据线之间的第二MOS晶体管 虚拟数据线，以及用于对第二虚拟数据线进行充电的第二负载电路。 存储装置还包括连接在第二数据线和虚拟数据线之间的第一均衡器电路，并且在半导体存储器件被设置为激活模式之后的预定时间段期间使两端的电位相等，以及第二均衡器电路 数据线和虚拟数据线，并且在存储器件被设置为活动模式之后的预定时间段期间两端的均衡电位。

公开(公告)号：US5124948A

公开(公告)日：1992-06-23

申请号：US751574

申请日：1991-08-22

申请人： Makoto Takizawa ,  Taira Iwase ,  Masamichi Asano ,  Yasunori Arime

发明人： Makoto Takizawa ,  Taira Iwase ,  Masamichi Asano ,  Yasunori Arime

IPC分类号： G11C29/00

CPC分类号： G11C29/822

摘要： A main memory cell array is divided into a plurality of blocks, and a spare memory cell group is arranged apart from the main memory cell array. The spare memory cell group uses bit lines or word lines different from those of the main memory cell array and includes spare memory cells which are different in structure from the memory cells of the main memory cell array. The number of the memory cells of the spare memory cell group is the same as that of the main memory cells of one row or column in each block of the main memory cell array, and data can be programmed into the spare memory cells after the completion of the manufacturing process. The operation of programming data into the spare memory cells of the spare memory cell array is effected by use of a write-in address buffer and a write-in decoder. When a row or column including a defective memory cell is designated in the main memory cell array, the row or column of the spare memory cells in the spare memory cell group is activated.

摘要翻译： 主存储单元阵列被分成多个块，并且备用存储单元组被布置成与主存储单元阵列分开。 备用存储单元组使用与主存储单元阵列不同的位线或字线，并且包括与主存储单元阵列的存储单元结构不同的备用存储单元。 备用存储单元组的存储单元的数量与主存储单元阵列的每个块中的一个行或列的主存储单元的数量相同，并且可以在完成后将数据编程到备用存储单元中 的制造过程。 通过使用写入地址缓冲器和写入解码器来实现将数据编程到备用存储单元阵列的备用存储单元中的操作。 当在主存储单元阵列中指定包括有缺陷存储单元的行或列时，备用存储单元组中的备用存储单元的行或列被激活。

公开(公告)号：US5067111A

公开(公告)日：1991-11-19

申请号：US426803

申请日：1989-10-26

申请人： Masamichi Asano ,  Hiroshi Iwahashi ,  Sadayuki Yokoyama

发明人： Masamichi Asano ,  Hiroshi Iwahashi ,  Sadayuki Yokoyama

IPC分类号： G06F11/18 ,  G11C16/26

CPC分类号： G06F11/183 ,  G06F11/187 ,  G11C16/26

摘要： A semiconductor memory device comprising a first Electrically Erasable Programmable Read Only Memory (EEPROM) cell array, a first row decoder, a first column decoder, two second EEPROM arrays each having a storage area equal in capacity to the specified storage area defined in the first EEPROM array, a second row decoder, a second column decoder, and a majority logic circuit. The first row decoder and the first column decoder access one of the memory cells of the first EEPROM array. The second row decoder and the second column decoder access one of the memory cells of either the second EEPROM array when one of the memory cells of first EEPROM array is accessed. The majority logic circuit carries out a majority logic operation on the data items read from the accessed memory cell of the first EEPROM array and the data items read from the accessed memory cells of the second EEPROM arrays, thereby to determine which data item is to be read out to an external device.

摘要翻译： 一种半导体存储器件，包括第一电可擦除可编程只读存储器（EEPROM）单元阵列，第一行解码器，第一列解码器，两个第二EEPROM阵列，每个第二EEPROM阵列的容量等于在第一 EEPROM阵列，第二行解码器，第二列解码器和多数逻辑电路。 第一行解码器和第一列解码器访问第一EEPROM阵列的存储单元之一。 当访问第一EEPROM阵列的存储单元之一时，第二行解码器和第二列解码器访问第二EEPROM阵列中的一个存储器单元。 多数逻辑电路对从第一EEPROM阵列的访问存储单元读取的数据项和从第二EEPROM阵列的访问存储单元读取的数据项进行多数逻辑运算，从而确定哪个数据项将是 读出外部设备。

公开(公告)号：US5055706A

公开(公告)日：1991-10-08

申请号：US311798

申请日：1989-02-17

申请人： Hiroto Nakai ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Shigeru Kumagai

发明人： Hiroto Nakai ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Shigeru Kumagai

IPC分类号： H01L21/8238 ,  G11C11/407 ,  G11C11/4076 ,  H01L27/092 ,  H01L27/10 ,  H03K5/00 ,  H03K5/1252 ,  H03K5/13 ,  H03K5/131 ,  H03K5/133 ,  H03K5/134 ,  H03K5/135

CPC分类号： H03K5/133 ,  H03K5/1252 ,  H03K2005/00195

摘要： A semiconductor integrated circuit including delay means for generating an output signal delayed by a predetermined time with respect to an input signal when a logic level of said input signal changes in a first direction. The delay means receives a control signal and generates an internal control signal which is delayed by a predetermined time with respect to the control signal when a logic level of the control signal changes in a first direction, including a capacitor for delaying the control signal and a resistor having one end and having the other end connected to the capacitor.

摘要翻译： 一种半导体集成电路，包括延迟装置，用于当所述输入信号的逻辑电平在第一方向上变化时，产生相对于输入信号延迟预定时间的输出信号。 当控制信号的逻辑电平在第一方向上变化时，延迟装置接收控制信号并产生相对于控制信号延迟预定时间的内部控制信号，包括用于延迟控制信号的电容器和 电阻器具有一端并且另一端连接到电容器。

公开(公告)号：US4799195A

公开(公告)日：1989-01-17

申请号：US168560

申请日：1988-03-04

申请人： Hiroshi Iwahashi ,  Masamichi Asano

发明人： Hiroshi Iwahashi ,  Masamichi Asano

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/28 ,  G11C29/00 ,  G11C29/12 ,  G11C11/40

CPC分类号： G11C16/28

摘要： A semiconductor memory device comprises memory cell transistors each having a double layered gate having a floating gate and a control gate. The memory device comprises a transistor for receiving a predetermined voltage from a source external to the memory device and providing it as a reference voltage in response to a control signal, and a sense amplifier for comparing a voltage dependent on the data read from the memory cell with the reference voltage.

摘要翻译： 半导体存储器件包括存储单元晶体管，每个存储单元晶体管具有一个具有浮置栅极和一个控制栅极的双层栅极。 存储器件包括晶体管，用于从存储器件外部的源接收预定电压并将其作为响应于控制信号的参考电压提供;以及读出放大器，用于根据从存储器单元读取的数据进行比较 具有参考电压。

公开(公告)号：US4725915A

公开(公告)日：1988-02-16

申请号：US717695

申请日：1985-03-29

申请人： Hiroshi Jwahashi ,  Masamichi Asano ,  Hiroshi Harada ,  Shinichi Tanaka ,  Hideki Sumihara

发明人： Hiroshi Jwahashi ,  Masamichi Asano ,  Hiroshi Harada ,  Shinichi Tanaka ,  Hideki Sumihara

IPC分类号： G11C16/10 ,  H01L27/02 ,  H01L27/088 ,  H01L29/78 ,  H03K3/353

CPC分类号： H01L27/0251 ,  G11C16/10 ,  H01L27/088

摘要： A semiconductor integrated circuit includes a MOS transistor, and a transistor circuit in which one end of a current path is connected to a drain of this MOS transistor and which has an avalanche breakdown voltage lower than a breakdown voltage of the MOS transistor.

摘要翻译： 半导体集成电路包括MOS晶体管和晶体管电路，其中电流路径的一端连接到该MOS晶体管的漏极，并且具有低于MOS晶体管的击穿电压的雪崩击穿电压。