公开(公告)号：US11929324B2

公开(公告)日：2024-03-12

申请号：US18133575

申请日：2023-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Park ,  Keunnam Kim ,  Sohyun Park ,  Jin-Hwan Chun ,  Wooyoung Choi ,  Sunghee Han ,  Inkyoung Heo ,  Yoosang Hwang

IPC: H01L23/48 ,  G11C5/10 ,  H01L21/768 ,  H01L23/52 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H10B12/00

CPC classification number: H01L23/528 ,  G11C5/10 ,  H01L21/76831 ,  H01L29/0649 ,  H01L29/4236 ,  H10B12/485

Abstract: The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

公开(公告)号：US11844212B2

公开(公告)日：2023-12-12

申请号：US17748261

申请日：2022-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Lee ,  Junsoo Kim ,  Hui-Jung Kim ,  Bong-Soo Kim ,  Satoru Yamada ,  Kyupil Lee ,  Sunghee Han ,  HyeongSun Hong ,  Yoosang Hwang

IPC: H10B41/27 ,  H01L23/532 ,  G11C7/18 ,  G11C8/14 ,  H10B41/35 ,  G11C11/404 ,  G11C11/4097 ,  H01L49/02

CPC classification number: H10B41/27 ,  G11C7/18 ,  G11C8/14 ,  H01L23/53295 ,  H01L28/60 ,  H10B41/35 ,  G11C11/404 ,  G11C11/4097

Abstract: A semiconductor memory device includes a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also includes a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer includes semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.

公开(公告)号：US20230337415A1

公开(公告)日：2023-10-19

申请号：US18337134

申请日：2023-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu Choi ,  Myeong-Dong Lee ,  Hyeon-Woo Jang ,  Keunnam Kim ,  Sooho Shin ,  Yoosang Hwang

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/315 ,  H10B12/0335

Abstract: Disclosed are a semiconductor memory device and a method of fabricating the same. The device includes a substrate including an active pattern with doped regions, a gate electrode crossing the active pattern between the doped regions, a bit line crossing the active pattern and being electrically connected to one of the doped regions, a spacer on a side surface of the bit line, a first contact coupled to another of the doped regions and spaced apart from the bit line with the spacer interposed therebetween, a landing pad on the first contact, and a data storing element on the landing pad. The another of the doped regions has a top surface, an upper side surface, and a curved top surface that extends from the top surface to the upper side surface. The first contact is in contact with the curved top surface and the upper side surface.

公开(公告)号：US11785763B2

公开(公告)日：2023-10-10

申请号：US17568440

申请日：2022-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wooyoung Choi ,  Juseong Oh ,  Yoosang Hwang

IPC: H01L21/768 ,  H10B12/00 ,  H01L49/02 ,  H01L23/522 ,  H01L23/528 ,  G11C5/10

CPC classification number: H10B12/37 ,  G11C5/10 ,  H01L23/528 ,  H01L23/5226 ,  H01L28/60

Abstract: A semiconductor device includes a substrate including a cell area having a first active region and a peripheral circuit area having a second active region, a direct contact contacting the first active region in the cell area, a bit line structure disposed on the direct contact, a capacitor structure electrically connected to the first active region, a gate structure disposed on the second active region in the peripheral circuit area, lower wiring layers disposed adjacent to the gate structure and electrically connected to the second active region, upper wiring layers disposed on the lower wiring layers, a wiring insulating layer disposed between the lower wiring layers and the upper wiring layers, and upper contact plugs connected to at least one of the lower wiring layers and the upper wiring layers and extending through the wiring insulating layer.

公开(公告)号：US11785761B2

公开(公告)日：2023-10-10

申请号：US17240486

申请日：2021-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hui-Jung Kim ,  Min Hee Cho ,  Bong-Soo Kim ,  Junsoo Kim ,  Satoru Yamada ,  Wonsok Lee ,  Yoosang Hwang

IPC: H10B12/00 ,  H01L21/28 ,  H01L29/49 ,  H01L29/06

CPC classification number: H10B12/34 ,  H01L21/28088 ,  H01L29/0649 ,  H01L29/4966 ,  H10B12/053 ,  H10B12/315 ,  H10B12/488

Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes an isolation layer in a first trench and a first gate electrode portion on the isolation layer. The semiconductor memory device includes a second gate electrode portion in a second trench. In some embodiments, the second gate electrode portion is wider, in a direction, than the first gate electrode portion. Moreover, in some embodiments, an upper region of the second trench is spaced apart from the first trench by a greater distance, in the direction, than a lower region of the second trench. Related methods of forming semiconductor memory devices are also provided.

公开(公告)号：US11776909B2

公开(公告)日：2023-10-03

申请号：US17205462

申请日：2021-03-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunjung Kim ,  Hui-Jung Kim ,  Keunnam Kim ,  Daeik Kim ,  Bong-soo Kim ,  Yoosang Hwang

IPC: H01L21/764 ,  H01L23/532 ,  H10B12/00 ,  H01L23/522 ,  H01L23/528 ,  H10B63/00

CPC classification number: H01L23/5329 ,  H01L21/764 ,  H01L23/5226 ,  H01L23/5283 ,  H10B12/0335 ,  H01L23/5222 ,  H10B12/315 ,  H10B63/30 ,  H10B63/80

Abstract: A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.

公开(公告)号：US20230225114A1

公开(公告)日：2023-07-13

申请号：US18124043

申请日：2023-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeik Kim ,  Bong-Soo Kim ,  Jemin Park ,  Taejin Park ,  Yoosang Hwang

IPC: H01L21/8234 ,  H10B12/00 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L21/823468 ,  H01L21/76829 ,  H01L21/76838 ,  H01L29/6656 ,  H10B12/31 ,  H10B12/482 ,  H01L21/3213

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure on the substrate. The stack structure includes a first insulating material and a second insulating material that is on the first insulating material. The semiconductor device includes a spacer that extends from a sidewall of the first insulating material of the stack structure to a portion of a sidewall of the second insulating material of the stack structure. Moreover, the semiconductor device includes a conductive line that is on the spacer. Methods of forming semiconductor devices are also provided.

公开(公告)号：US11538861B2

公开(公告)日：2022-12-27

申请号：US17167851

申请日：2021-02-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hui-Jung Kim ,  Kiseok Lee ,  Keunnam Kim ,  Yoosang Hwang

IPC: H01L47/00 ,  H01L27/24 ,  H01L45/00 ,  H01L43/08

Abstract: Disclosed is a variable resistance memory device including a first conductive line extending in a first direction parallel to a top surface of the substrate, memory cells spaced apart from each other in the first direction on a side of the first conductive line and connected to the first conductive line, and second conductive lines respectively connected to the memory cells. Each second conductive line is spaced apart in a second direction from the first conductive line. The second direction is parallel to the top surface of the substrate and intersects the first direction. The second conductive lines extend in a third direction perpendicular to the top surface of the substrate and are spaced apart from each other in the first direction. Each memory cell includes a variable resistance element and a select element that are positioned at a same level horizontally arranged in the second direction.

公开(公告)号：US20220344344A1

公开(公告)日：2022-10-27

申请号：US17720664

申请日：2022-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Park ,  Taehoon Kim ,  Kyujin Kim ,  Chulkwon Park ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L27/108

Abstract: An integrated circuit device includes a substrate having an active region and a word line trench therein. The word line trench includes a lower portion having a first width, and an upper portion, which extends between the lower portion and a surface of the substrate and has a second width that is greater than the first width. A word line is provided, which extends in and adjacent a bottom of the word line trench. A gate insulation layer is provided, which extends between the word line and sidewalls of the lower portion of the word line trench. An electrically insulating gate capping layer is provided in the upper portion of the word line trench. An insulation liner is provided, which extends between the gate capping layer and sidewalls of the upper portion of the word line trench. The gate insulation layer extends between the insulation liner and a portion of the gate capping layer, which extends within the upper portion of the word line trench.

公开(公告)号：US11355509B2

公开(公告)日：2022-06-07

申请号：US17000857

申请日：2020-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Lee ,  Junsoo Kim ,  Hui-Jung Kim ,  Bong-Soo Kim ,  Satoru Yamada ,  Kyupil Lee ,  Sunghee Han ,  Hyeongsun Hong ,  Yoosang Hwang

IPC: H01L27/11556 ,  H01L23/532 ,  G11C7/18 ,  H01L49/02 ,  G11C8/14 ,  H01L27/11524 ,  G11C11/404 ,  G11C11/4097

Abstract: A semiconductor memory device comprises a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also comprises a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer comprises semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.