公开(公告)号：US20060290402A1

公开(公告)日：2006-12-28

申请号：US11511647

申请日：2006-08-29

申请人： Vasisht Vadi ,  Steven Young ,  Atul Ghia ,  Adebabay Bekele ,  Suresh Menon

发明人： Vasisht Vadi ,  Steven Young ,  Atul Ghia ,  Adebabay Bekele ,  Suresh Menon

IPC分类号： G06F1/04

CPC分类号： G06F1/10 ,  H03K5/15013 ,  H03K19/1774 ,  H03K19/17784 ,  H03K19/17796

摘要： A clock distribution network having: a backbone clock signal line configured to provide a differential clock signal; multiple branches coupled to the backbone clock signal line for distributing the differential clock signal to multiple programmable function elements; a first leaf node coupled to a first branch, where the first leaf node is configured to provide the differential clock signal to a first programmable function element; and a second leaf node coupled to a second branch, where the second leaf node is configured to provide a single ended clock signal derived from the differential clock signal to a second programmable function element.

公开(公告)号：US20060146457A1

公开(公告)日：2006-07-06

申请号：US11027414

申请日：2004-12-30

申请人： Albert Lu ,  Steven Young

发明人： Albert Lu ,  Steven Young

IPC分类号： H02H9/00

CPC分类号： H03K17/165 ,  H03K17/0822

摘要： An output driver having electrostatic discharge (ESD) protection is disclosed. The output driver includes a first gain transistor, a second gain transistor, a capacitor and a resistor. The first gain transistor provides a first stage gain, and the second gain transistor provides a second stage gain. The capacitor, which is connected to the first and second gain transistors, provides a compensation function between the first and second gain transistors during normal operations. In response to an occurrence of an ESD event at the output of the output driver, the capacitor turns on the second gain transistor The resistor, which is also connected to the first and second gain transistors, returns the second gain transistor to normal operations after the occurrence of an ESD event.

公开(公告)号：US20060042211A1

公开(公告)日：2006-03-02

申请号：US10933024

申请日：2004-09-02

申请人： David Heinsey ,  Michael Digman ,  Steven Young

发明人： David Heinsey ,  Michael Digman ,  Steven Young

IPC分类号： A01D75/18

CPC分类号： A01F12/16

摘要： A stone detection system of a harvester that automatically changes its sensitivity to signals from a stone sensor in response to the type of harvesting equipment connected to the harvester is provided. The stone detection system generally includes a stone sensor, a header sensor and a microprocessor. The stone sensor is configured to generate a signal indicative of the presence of a stone in the crop harvesting system. The header sensor is disposed on the crop harvesting system to sense the header type and to generate a signal indicating the header type. The microprocessor is coupled to the stone sensor and the header sensor to process the stone sensor signal based at least in part upon the header sensor signal.

摘要翻译： 提供了收割机的石探测系统，其响应于连接到收割机的收获设备的类型而自动地改变其对来自石传感器的信号的敏感度。 石检测系统通常包括石传感器，标头传感器和微处理器。 石传感器被配置为产生指示作物收获系统中石头存在的信号。 头部传感器设置在作物收获系统上以感测头部类型并产生指示头部类型的信号。 微处理器耦合到石传感器和标头传感器，以至少部分地基于标题传感器信号来处理石传感器信号。

公开(公告)号：US20060014200A1

公开(公告)日：2006-01-19

申请号：US11225247

申请日：2005-09-12

申请人： William McMillan ,  Lee Christel ,  David Borkholder ,  Steven Young

发明人： William McMillan ,  Lee Christel ,  David Borkholder ,  Steven Young

IPC分类号： C12Q1/68 ,  C12M1/34

CPC分类号： C12Q1/6851 ,  B01L7/52 ,  G01N21/274 ,  G01N21/278 ,  G01N21/6428 ,  G01N21/645 ,  G01N2021/6417 ,  G01N2021/6419 ,  G01N2021/6421 ,  G01N2021/6432 ,  G01N2021/6439 ,  G01N2021/6441 ,  G01N2021/6463 ,  G01N2021/6471 ,  G01N2035/00366 ,  G01N2035/00376 ,  G01N2035/0097 ,  G01N2201/062 ,  G01N2201/0627 ,  C12Q2537/165 ,  C12Q2545/107 ,  C12Q2545/113 ,  C12Q2545/101

摘要： An apparatus for determining a threshold value (e.g., a threshold cycle number or a time value) in a nucleic acid amplification reaction comprises a detection mechanism for measuring, at a plurality of different times during the amplification reaction, at least one signal whose intensity is related to the quantity of a nucleic acid sequence being amplified in the reaction. A controller in communication with the detection mechanism is programmed to store signal values defining a growth curve for the nucleic acid sequence, determine a derivative of the growth curve, and calculate a cycle number or time value associated with a characteristic of the derivative.

公开(公告)号：US20050144216A1

公开(公告)日：2005-06-30

申请号：US11019854

申请日：2004-12-21

申请人： James Simkins ,  Steven Young ,  Jennifer Wong ,  Bernard New ,  Alvin Ching

发明人： James Simkins ,  Steven Young ,  Jennifer Wong ,  Bernard New ,  Alvin Ching

IPC分类号： G06F7/509 ,  G06F15/00

CPC分类号： G06F7/509

摘要： Described are arithmetic circuits divided logically into a product generator and an adder. Multiplexing circuitry logically disposed between the product generator and the adder supports conventional functionality by providing partial products from the product generator to addend terminals of the adder. The multiplexing circuitry can also be controlled to direct a number of external added inputs to the adder. The additional addend inputs can include inputs and outputs cascaded from other arithmetic circuits.

摘要翻译： 描述的是算术电路，逻辑上分为乘积发生器和加法器。 逻辑上位于产品发生器和加法器之间的多路复用电路通过提供来自产品发生器的部分乘积到加法器的末端来支持常规功能。 还可以控制复用电路以将多个外部添加的输入引导到加法器。 附加加数输入可以包括从其他算术电路级联的输入和输出。

公开(公告)号：US20050144215A1

公开(公告)日：2005-06-30

申请号：US11019518

申请日：2004-12-21

申请人： James Simkins ,  Steven Young ,  Jennifer Wong ,  Bernard New ,  Alvin Ching

发明人： James Simkins ,  Steven Young ,  Jennifer Wong ,  Bernard New ,  Alvin Ching

IPC分类号： G06F15/00

CPC分类号： G06F7/5443

摘要： In one embodiment an IC is disclosed which includes a plurality of cascaded digital signal processing slices, wherein each slice has a multiplier coupled to an adder via a multiplexer and each slice has a direct connection to an adjoining slice; and means for configuring the plurality of digital signal processing slices to perform one or more mathematical operations, via, for example, opmodes. This IC allows for the implementation of some basic math functions, such as add, subtract, multiply and divide. Many other applications may be implemented using the one or more DSP slices, for example, accumulate, multiply accumulate (MACC), a wide multiplexer, barrel shifter, counter, and folded, decimating, and interpolating FIRs to name a few.

摘要翻译： 在一个实施例中，公开了一种IC，其包括多个级联的数字信号处理片，其中每个片具有经由多路复用器耦合到加法器的乘法器，并且每个片与直接连接到相邻片; 以及用于通过例如opmode来配置多个数字信号处理片以执行一个或多个数学运算的装置。 该IC允许实现一些基本的数学函数，例如加，减，乘和除。 可以使用一个或多个DSP片段来实现许多其它应用，例如，累加，乘法累加（MACC），宽多路复用器，桶形移位器，计数器和折叠，抽取和内插FIR等等。

公开(公告)号：US20050144213A1

公开(公告)日：2005-06-30

申请号：US11019853

申请日：2004-12-21

申请人： James Simkins ,  Steven Young ,  Jennifer Wong ,  Bernard New ,  Alvin Ching

发明人： James Simkins ,  Steven Young ,  Jennifer Wong ,  Bernard New ,  Alvin Ching

IPC分类号： G06F7/499 ,  G06F15/00

CPC分类号： G06F7/49963

摘要： Described are mathematical circuits that perform flexible rounding schemes. The circuits require few additional resources and can be adjusted dynamically to change the number of bits involved in the rounding. In one embodiment, a DSP circuit stores a rounding constant selected from the group of binary numbers 2(M−1) and 2(M−1)−1, calculates a correction factor, and sums the rounding constant, the correction factor, and a data item to obtain a rounded data item.

摘要翻译： 描述了执行灵活舍入方案的数学电路。 这些电路需要很少的额外资源，并且可以动态调整以改变舍入所涉及的位数。 在一个实施例中，DSP电路存储从二进制数2（M-1）和2（M-1）-1组中选出的舍入常数，计算一个 校正因子，并且舍入常数，校正因子和数据项，以获得舍入的数据项。

公开(公告)号：US20050144211A1

公开(公告)日：2005-06-30

申请号：US11019782

申请日：2004-12-21

申请人： James Simkins ,  Steven Young ,  Jennifer Wong ,  Bernard New ,  Alvin Ching

发明人： James Simkins ,  Steven Young ,  Jennifer Wong ,  Bernard New ,  Alvin Ching

IPC分类号： G06F15/00 ,  H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17732

摘要： Described is a programmable logic device (PLD) with columns of DSP slices that can be combined to create DSP circuits of varying size and complexity. DSP slices in accordance with some embodiments includes programmable operand input registers that can be configured to introduce different amounts of delay, from zero to two clock cycles, for example, to support pipelining. In one such embodiment, each DSP slice includes a partial-product generator having a multiplier port, a multiplicand port, and a product port. The multiplier and multiplicand ports connect to the operand input port via respective first and second operand input registers, each of which is capable of introducing from zero to two clock cycles of delay. In another embodiment, the output of at least one operand input register can connect to the input of an operand input register of a downstream DSP slice so that operands can be transferred among one or more slices.

摘要翻译： 描述了可编程逻辑器件（PLD），其具有可以组合的DSP片段，以创建不同大小和复杂度的DSP电路。 根据一些实施例的DSP片段包括可被配置为从零到两个时钟周期引入不同量的延迟的可编程操作数输入寄存器，例如以支持流水线化。 在一个这样的实施例中，每个DSP片包括具有乘法器端口，被乘数端口和产品端口的部分乘积生成器。 乘法器和被乘数端口通过相应的第一和第二操作数输入寄存器连接到操作数输入端口，每个第一和第二操作数输入寄存器能够从零延迟到两个延迟的时钟周期。 在另一个实施例中，至少一个操作数输入寄存器的输出可以连接到下游DSP片的操作数输入寄存器的输入，使得操作数可以在一个或多个片之间传送。

公开(公告)号：US20050007155A1

公开(公告)日：2005-01-13

申请号：US10683944

申请日：2003-10-10

申请人： Steven Young

发明人： Steven Young

IPC分类号： G06F17/50 ,  H01L27/02 ,  H01L27/118 ,  H03K19/177

CPC分类号： H01L27/11898 ,  H01L27/0207 ,  H01L27/11803 ,  H01L27/11807

摘要： An integrated circuit (IC) is disclosed having circuitry arranged in a plurality of columns. A column in the IC is essentially a series of aligned circuit elements of the same type that extends from a first edge of the IC to a second edge. In addition there may be a center column having circuit elements of different types.

摘要翻译： 公开了一种集成电路（IC），其具有布置在多个列中的电路。 IC中的列基本上是从IC的第一边缘延伸到第二边缘的相同类型的一系列对准的电路元件。 此外，可以存在具有不同类型的电路元件的中心列。

公开(公告)号：US5330910A

公开(公告)日：1994-07-19

申请号：US415432

申请日：1989-09-27

申请人： Steven Young ,  Joseph L. Witztum ,  Linda K Curtiss

发明人： Steven Young ,  Joseph L. Witztum ,  Linda K Curtiss

IPC分类号： G01N33/53 ,  C07K14/005 ,  C07K14/195 ,  C07K16/00 ,  C07K16/18 ,  C07K19/00 ,  C12N5/10 ,  C12N15/02 ,  C12P21/00 ,  C12P21/08 ,  C12R1/91 ,  G01N33/577 ,  C12N5/12 ,  C07K15/28

CPC分类号： C07K16/18 ,  C07K2317/77

摘要： Two hybridomas that produce receptors containing antibody combining sites that immunoreact with apolipoprotein B-100 are disclosed as are uses for the receptors, compositions and diagnostic systems that include the receptors.

摘要翻译： 公开了产生含有与载脂蛋白B-100免疫反应的抗体结合位点的受体的两个杂交瘤作为包括受体的受体，组合物和诊断系统的用途。