Method of making a solid state inductor
    71.
    发明授权
    Method of making a solid state inductor 失效
    制作固态电感的方法

    公开(公告)号:US06876521B2

    公开(公告)日:2005-04-05

    申请号:US10705066

    申请日:2003-11-10

    摘要: A solid-state inductor and a method for forming a solid-state inductor are provided. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) thin film overlying the bottom electrode; forming a top electrode overlying the CMR thin film; applying an electrical field treatment to the CMR thin film in the range of 0.4 to 1 megavolts per centimeter (MV/cm) with a pulse width in the range of 100 nanoseconds (ns) to 1 millisecond (ms); in response to the electrical field treatment, converting the CMR thin film into a CMR thin film inductor; applying a bias voltage between the top and bottom electrodes; and, in response to the applied bias voltage, creating an inductance between the top and bottom electrodes. When the applied bias voltage is varied, the inductance varies in response.

    摘要翻译: 提供固态电感器和形成固态电感器的方法。 该方法包括:形成底部电极; 形成覆盖底部电极的巨大磁阻(CMR)薄膜; 形成覆盖CMR薄膜的顶部电极; 以0.1纳秒(ns)至1毫秒(ms)的脉冲宽度在0.4至1兆伏特/厘米(MV / cm)范围内对CMR薄膜进行电场处理; 响应于电场处理,将CMR薄膜转换成CMR薄膜电感器; 在顶部和底部电极之间施加偏置电压; 并且响应于施加的偏置电压,在顶部和底部电极之间产生电感。 当施加的偏置电压变化时,电感响应变化。

    Copper metal precursor
    72.
    发明授权
    Copper metal precursor 失效
    铜金属前体

    公开(公告)号:US06764537B2

    公开(公告)日:2004-07-20

    申请号:US10453829

    申请日:2003-06-02

    IPC分类号: C23C1618

    CPC分类号: H01L21/28556 C23C16/18

    摘要: A method for chemical vapor deposition of copper metal thin film on a substrate includes heating a substrate onto which the copper metal thin film is to be deposited in a chemical vapor deposition chamber; vaporizing a precursor containing the copper metal, wherein the precursor is a compound of (&agr;-methylstyrene)Cu(I)(hfac), where hfac is hexafluoroacetylacetonate, and (hfac)Cu(I)L, where L is an alkene; introducing the vaporized precursor into the chemical vapor deposition chamber adjacent the heated substrate; and condensing the vaporized precursor onto the substrate thereby depositing copper metal onto the substrate. A copper metal precursor for use in the chemical vapor deposition of a copper metal thin film is a compound of (&agr;-methylstyrene)Cu(I)(hfac), where hfac is hexafluoroacetylacetonate, and (hfac)Cu(I)L, where L is an alkene taken from the group of alkenes consisting of 1-pentene, 1-hexene and trimethylvinylsilane.

    摘要翻译: 铜基金属薄膜在基板上进行化学气相沉积的方法包括在化学气相沉积室中加热要沉积铜金属薄膜的基板; 蒸发含有铜金属的前体,其中前体是(α-甲基苯乙烯)Cu(I)(hfac)的化合物,其中hfac是六氟乙酰丙酮化物,和(hfac)Cu(I)L,其中L是烯烃; 将蒸发的前体引入与加热的基底相邻的化学气相沉积室; 并将蒸发的前体冷凝到基底上,从而将铜金属沉积到基底上。 用于铜金属薄膜的化学气相沉积的铜金属前体是(α-甲基苯乙烯)Cu(I)(hfac)的化合物,其中hfac是六氟乙酰丙酮化物,和(hfac)Cu(I)L,其中 L是从由1-戊烯,1-己烯和三甲基乙烯基硅烷组成的烯烃族中获得的烯烃。

    Electrically programmable resistance cross point memory
    75.
    发明授权
    Electrically programmable resistance cross point memory 有权
    电可编程电阻交叉点存储器

    公开(公告)号:US06531371B2

    公开(公告)日:2003-03-11

    申请号:US09894922

    申请日:2001-06-28

    IPC分类号: H01L2120

    摘要: Resistive cross point memory devices are provided, along with methods of manufacture and use. The memory device comprises an active layer of perovskite material interposed between upper electrodes and lower electrodes. A bit region located within the active layer at the cross point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. Memory circuits are provided to aid in the programming and read out of the bit region.

    摘要翻译: 提供了电阻式交叉点存储器件以及制造和使用方法。 存储器件包括插在上电极和下电极之间的钙钛矿材料的有源层。 在上电极和下电极的交叉点处位于有源层内的位区域具有响应于施加一个或更多个电压脉冲而可以在值范围内变化的电阻率。 可以使用电压脉冲来增加比特区域的电阻率,降低比特区域的电阻率,或者确定比特区域的电阻率。 提供存储器电路以帮助编程和读出位区域。

    Precursors for zirconium and hafnium oxide thin film deposition
    76.
    发明授权
    Precursors for zirconium and hafnium oxide thin film deposition 有权
    锆和氧化铪薄膜沉积的前体

    公开(公告)号:US06472337B1

    公开(公告)日:2002-10-29

    申请号:US10020471

    申请日:2001-10-30

    IPC分类号: H01L2131

    摘要: A method of making a precursor for a thin film formed by chemical vapor deposition processes, includes mixing ZCl4 with H(tmhd)3 solvent and benzene to form a solution, where Z is an element taken from the group of elements consisting of hafnium and zirconium; refluxing the solution for twelve hours in an argon atmosphere; removing the solvents via vacuum, thereby producing a solid compound; and sublimating the compound at 200° C. in a near vacuum of 0.1 mmHg. A ZOx precursor, for use in a chemical vapor deposition process, includes a Z-containing compound taken from the group of compounds consisting of ZCl(tmhd)3 and ZCl2(tmhd)2.

    摘要翻译: 通过化学气相沉积法制备薄膜前体的方法包括将ZCl4与H(tmhd)3溶剂和苯混合形成溶液,其中Z是从由铪和锆组成的元素组成的元素 ; 在氩气氛中回流12小时; 通过真空除去溶剂,从而产生固体化合物; 并在0.1mmHg的接近真空下在200℃升华该化合物。 用于化学气相沉积方法的ZOx前体包括从ZCl(tmhd)3和ZCl 2(tmhd)2组成的化合物组中取代的含Z化合物。

    Self-aligned cross point resistor memory array
    78.
    发明授权
    Self-aligned cross point resistor memory array 有权
    自对准交叉点电阻存储器阵列

    公开(公告)号:US07323349B2

    公开(公告)日:2008-01-29

    申请号:US11120385

    申请日:2005-05-02

    IPC分类号: H01L21/00 H01L21/8242

    摘要: A method of fabricating resistor memory array includes preparing a silicon substrate; depositing a bottom electrode, a sacrificial layer, and a hard mask layer on a substrate P+ layer; masking, patterning and etching to remove, in a first direction, a portion of the hard mask, the sacrificial material, the bottom electrode; depositing a layer of silicon oxide; masking, patterning and etching to remove, in a second direction perpendicular to the first direction, a portion of the hard mask, the sacrificial material, the bottom electrode;, and over etching to an N+ layer and at least 100 nm of the silicon substrate; depositing of a layer of silicon oxide; etching to remove any remaining hard mask and any remaining sacrificial material; depositing a layer of CMR material; depositing a top electrode; applying photoresist, patterning the photoresist and etching the top electrode; and incorporating the memory array into an integrated circuit.

    摘要翻译: 制造电阻器存储器阵列的方法包括制备硅衬底; 在衬底P +层上沉积底部电极,牺牲层和硬掩模层; 掩模,图案化和蚀刻以在第一方向上去除硬掩模,牺牲材料,底部电极的一部分; 沉积一层氧化硅; 掩模,图案化和蚀刻以在垂直于第一方向的第二方向上去除硬掩模,牺牲材料,底部电极的一部分,并且对N +层和至少100nm的硅衬底进行过蚀刻 ; 沉积一层氧化硅; 蚀刻以除去任何剩余的硬掩模和任何剩余的牺牲材料; 沉积一层CMR材料; 沉积顶部电极; 施加光致抗蚀剂,图案化光致抗蚀剂并蚀刻顶部电极; 并将存储器阵列并入集成电路中。

    Cross-point resistor memory array
    79.
    发明授权
    Cross-point resistor memory array 有权
    交叉点电阻存储器阵列

    公开(公告)号:US07193267B2

    公开(公告)日:2007-03-20

    申请号:US10971204

    申请日:2004-10-21

    IPC分类号: H01L29/76

    摘要: Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions. The resistive cross-point memory device is formed by doping lines within a substrate one polarity, and then doping regions of the lines the opposite polarity to form diodes. Bottom electrodes are then formed over the diodes with a layer of resistive memory material overlying the bottom electrodes. Top electrodes may then be added at an angled to form a cross-point array defined by the lines and the top electrodes.

    摘要翻译: 提供了电阻式交叉点存储器件,以及制造和使用方法。 存储器件由介于上电极和下电极之间的电阻存储器材料的有源层组成。 在上电极和下电极的交叉点处位于电阻性存储器材料内的位区域具有响应于施加一个或更多个电压脉冲而能够在一定范围内变化的电阻率。 可以使用电压脉冲来增加比特区域的电阻率,降低比特区域的电阻率,或者确定比特区域的电阻率。 在电阻性存储器材料和下电极之间的界面处形成二极管,其可以形成为掺杂区域。 电阻性交叉点存储器件通过在衬底内掺杂一个极性而形成,然后将相反极性的线的掺杂区域形成二极管。 然后在二极管上形成一层电阻记忆材料覆盖底部电极的底部电极。 然后可以以倾斜的角度添加顶部电极以形成由线和顶部电极限定的交叉点阵列。

    Single-phase c-axis doped PGO ferroelectric thin films
    80.
    发明授权
    Single-phase c-axis doped PGO ferroelectric thin films 有权
    单相c轴掺杂PGO铁电薄膜

    公开(公告)号:US07009231B2

    公开(公告)日:2006-03-07

    申请号:US11046620

    申请日:2005-01-28

    IPC分类号: H01L29/94

    摘要: A method for forming a doped PGO ferroelectric thin film, and related doped PGO thin film structures are described. The method comprising: forming either an electrically conductive or electrically insulating substrate; forming a doped PGO film overlying the substrate; annealing; crystallizing; and, forming a single-phase c-axis doped PGO thin film overlying the substrate, having a Curie temperature of greater than 200 degrees C. Forming a doped PGO film overlying the substrate includes depositing a doped precursor in the range between 0.1N and 0.5N, with a molecular formula of Pby-xMxGe3O11, where: M is a doping element; y=4.5 to 6; and, x=0.1 to 1. The element M can be Sn, Ba, Sr, Cd, Ca, Pr, Ho, La, Sb, Zr, or Sm.

    摘要翻译: 描述了用于形成掺杂的PGO铁电薄膜的方法以及相关的掺杂PGO薄膜结构。 该方法包括:形成导电或电绝缘的衬底; 在衬底上形成掺杂的PGO膜; 退火; 结晶 并且形成覆盖在衬底上的单相c轴掺杂的PGO薄膜,其居里温度大于200℃。形成覆盖在衬底上的掺杂PGO膜包括在0.1N和0.5之间的范围内沉积掺杂的前体 N,具有分子式为Pb x Si x N x N x O 11,其中:M是掺杂物 元件; y = 4.5〜6; x = 0.1〜1。元素M可以是Sn,Ba,Sr,Cd,Ca,Pr,Ho,La,Sb,Zr或Sm。