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    System And Method For Managing Peak Power Demand And Noise In Non-volatile Memory Array
    77.
    发明申请
    System And Method For Managing Peak Power Demand And Noise In Non-volatile Memory Array 审中-公开

    公开(公告)号：US20190295647A1

    公开(公告)日：2019-09-26

    申请号：US16015020

    申请日：2018-06-21

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Vipin Tiwari ,  Hieu Van Tran ,  Nhan Do ,  Mark Reiten

    IPC: G11C16/04 ,  H01L29/423 ,  H01L29/788 ,  H01L27/11521

    Abstract: A memory device includes rows and columns of memory cells, word lines each connected to a memory cell row, bit lines each connected to a memory cell column, a word line driver connected to the word lines, a bit line driver connected to the bit lines, word line switches each disposed on one of the word lines for selectively connecting one memory cell row to the word line driver, and bit line switches each disposed on one of the bit lines for selectively connecting one memory cell column to the bit line driver. A controller controls the word line switches to connect only some of the rows of memory cells to the word line driver at a first point in time, and controls the bit line switches to connect only some of the columns of memory cells to the bit line driver at a second point in time.

    System and method for generating random numbers based on non-volatile memory cell array entropy
    78.
    发明授权
    System and method for generating random numbers based on non-volatile memory cell array entropy 有权

    公开(公告)号：US10381088B2

    公开(公告)日：2019-08-13

    申请号：US15905720

    申请日：2018-02-26

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Vipin Tiwari ,  Mark Reiten

    IPC: G11C16/24 ,  H01L27/11521 ,  G06F7/58 ,  G11C16/28 ,  G11C16/04 ,  G11C16/22 ,  H01L29/423

    Abstract: A memory device that generates a unique identifying number, and includes a plurality of memory cells and a controller. Each of the memory cells includes first and second regions formed in a semiconductor substrate, wherein a channel region of the substrate extends between the first and second regions, a floating gate disposed over and insulated from a first portion of the channel region, and a select gate disposed over and insulated from a second portion of the channel region. The controller is configured to apply one or more positive voltages to the first regions of the memory cells while the memory cells are in a subthreshold state for generating leakage current through each of the channel regions, measure the leakage currents, and generate a number based on the measured leakage currents.

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