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公开(公告)号：US20090169789A1
公开(公告)日：2009-07-02
申请号：US12318341
申请日：2008-12-24
申请人： Tadahiro Ohmi , Akinobu Teramoto , Keita Fushimi , Jiro Yamanaka , Masayuki Miyashita , Tomoharu Nishioka
发明人： Tadahiro Ohmi , Akinobu Teramoto , Keita Fushimi , Jiro Yamanaka , Masayuki Miyashita , Tomoharu Nishioka
IPC分类号： B32B1/08
CPC分类号： B32B27/28 , B32B1/08 , B32B27/34 , Y10T428/1393
摘要： A resin pipe has an inner layer made of a fluororesin, an intermediate layer of nylon, and an outermost layer made of a fluororesin and covering the intermediate layer.
摘要翻译： 树脂管具有由氟树脂制成的内层，尼龙的中间层和由氟树脂制成的最外层并覆盖中间层。
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公开(公告)号：US20090120673A1
公开(公告)日：2009-05-14
申请号：US11990860
申请日：2006-08-18
IPC分类号： H05K1/00
CPC分类号： H05K1/024 , H05K3/4602 , H05K3/4626 , H05K3/4673 , H05K2201/0116 , H05K2201/0195 , H05K2201/0209 , H05K2201/0254
摘要： A multilayered circuit board which is provided with a low-permittivity interlayer insulating film, and which can significantly improve the performance such as signal transmission characteristics of the multilayered circuit board such as a package and a printed board, because the surface in contact with the interlayer insulating film of the circuit board has no unevenness to eliminate the lowering of production yield and the deterioration of high-frequency signal transmission characteristics; and electronic equipment using the circuit board. The multilayered circuit board comprises, mounted on a substrate, plural wiring layers and plural insulating layers positioned between the plural wiring layers, wherein at least part of the plural insulating layers are composed of a porous insulating layer containing at least any of materials selected from a porous material group consisting of porous material, aerogel, porous silica, porous polymer, hollow silica and hollow polymer, and a non-porous insulating layer formed on at least one surface of the porous insulating layer and not containing the porous material group.
摘要翻译： 具有低介电常数层间绝缘膜的多层电路板，能够显着地提高诸如封装和印刷电路板的多层电路板的信号传输特性等性能，因为与中间层 电路板的绝缘膜没有不均匀性，消除了生产成本的降低和高频信号传输特性的恶化; 和使用电路板的电子设备。 多层电路板包括安装在基板上的多个布线层和位于多个布线层之间的多个绝缘层，其中多个绝缘层的至少一部分由多孔绝缘层组成，多孔绝缘层至少含有选自 由多孔材料，气凝胶，多孔二氧化硅，多孔聚合物，中空二氧化硅和中空聚合物组成的多孔材料组和形成在多孔绝缘层的至少一个表面上并且不包含多孔材料组的无孔绝缘层。
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公开(公告)号：US20090108452A1
公开(公告)日：2009-04-30
申请号：US12290589
申请日：2008-10-31
申请人： Takenao Nemoto , Akinobu Teramoto , Tadahiro Ohmi
发明人： Takenao Nemoto , Akinobu Teramoto , Tadahiro Ohmi
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/53238 , C23C14/0641 , C23C14/345 , H01L21/2855 , H01L21/76843 , H01L21/76846 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device including a sputtering process for forming a barrier film mainly having tantalum or tantalum nitride on an interlayer insulator formed by sputtering using a xenon gas. The sputtering process may include a step of forming one barrier film mainly composed of tantalum nitride on a substrate by sputtering using a xenon gas by applying a RF bias, and a step for forming another barrier film mainly composed of tantalum on the first barrier film by sputtering using a xenon gas without applying the RF bias. The barrier film may be formed by changing the RF bias continuously, and forming the interlayer insulator side by applying the RF bias, and forming the wiring side without applying the RF bias.
摘要翻译： 一种制造半导体器件的方法，该半导体器件包括溅射工艺，用于在通过使用氙气的溅射形成的层间绝缘体上形成主要具有钽或氮化钽的阻挡膜。 溅射工艺可以包括通过施加RF偏压通过使用氙气气体的溅射在衬底上形成主要由氮化钽构成的一个阻挡膜的步骤，以及用于在第一阻挡膜上形成主要由钽构成的另一阻挡膜的步骤 使用氙气进行溅射而不施加RF偏压。 可以通过连续地改变RF偏压来形成阻挡膜，并且通过施加RF偏压来形成层间绝缘体侧，并且在不施加RF偏压的情况下形成布线侧。
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公开(公告)号：US20090001471A1
公开(公告)日：2009-01-01
申请号：US12086886
申请日：2006-12-20
IPC分类号： H01L29/00
CPC分类号： H01L27/1211 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L29/045 , H01L29/785 , H01L2029/7857
摘要： For equalizing the rising and falling operating speeds in a CMOS circuit, it is necessary to make the areas of a p-type MOS transistor and an n-type MOS transistor different from each other due to a difference in carrier mobility therebetween. This area unbalance prevents an improvement in integration degree of semiconductor devices.The NMOS transistor and the PMOS transistor each have a three-dimensional structure with a channel region on both the (100) plane and the (110) plane so that the areas of the channel regions and gate insulating films of both transistors are equal to each other. Accordingly, it is possible to make the areas of the gate insulating films and so on equal to each other and also to make the gate capacitances equal to each other. Further, the integration degree on a substrate can be improved twice as much as that in the conventional technique.
摘要翻译： 为了均衡CMOS电路中的上升和下降操作速度，由于它们之间的载流子迁移率的差异，需要使p型MOS晶体管和n型MOS晶体管的面积彼此不同。 该区域不平衡防止了半导体器件的集成度的提高。 NMOS晶体管和PMOS晶体管各自具有在（100）面和（110）面上具有沟道区的三维结构，使得两个晶体管的沟道区和栅绝缘膜的面积等于 其他。 因此，可以使栅极绝缘膜等的面积相等并且使栅极电容彼此相等。 此外，基板上的积分度可以提高到常规技术的两倍。
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75.发明申请公开(公告)号：US20080268657A1
公开(公告)日：2008-10-30
申请号：US10594895
申请日：2005-03-31
IPC分类号： H01L21/469 , H05H1/24
CPC分类号： H01L21/3105 , H01J2237/3387 , H01L21/28273 , H01L21/28282 , H01L21/3143 , H01L27/115 , H01L27/11521 , H01L27/11568
摘要： The application of oxynitriding treatment to electronic appliances involve the problem that N2 ions are formed to thereby damage any oxynitride film. It is intended to provide a method of plasma treatment capable of realizing high-quality oxynitriding and to provide a process for producing an electronic appliance in which use is made of the method of plasma treatment. There is provided a method of plasma treatment, comprising generating plasma with a gas for plasma excitation and introducing a treating gas in the plasma to thereby treat a treatment subject, wherein the treating gas contains nitrous oxide gas, this nitrous oxide gas introduced in a plasma of
摘要翻译： 对电子器件应用氧氮化处理涉及形成N 2+离子从而损坏任何氮氧化物膜的问题。 旨在提供能够实现高质量氮氧化的等离子体处理方法，并提供一种使用等离子体处理方法的电子设备的制造方法。 提供了一种等离子体处理方法，包括用等离子体激发的气体产生等离子体并在等离子体中引入处理气体，从而处理处理对象，其中处理气体含有一氧化二氮气体，这种一氧化二氮气体引入等离子体 的<2.24eV电子温度，从而降低了任何绝缘膜损伤的离子的产生，从而实现高质量的氮氧化。 此外，提供了一种使用等离子体处理方法的电子设备的制造方法。
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公开(公告)号：US20070052042A1
公开(公告)日：2007-03-08
申请号：US10551843
申请日：2004-03-31
IPC分类号： H01L29/94 , H01L21/8238
CPC分类号： H01L21/318 , H01L21/28167 , H01L21/28194 , H01L21/28202 , H01L29/513 , H01L29/518
摘要： In order to provide a semiconductor device having good quality by keeping the relative permittivity of a High-K insulation film in a high state, or to provide a method for manufacturing a semiconductor device in which the relative permittivity of the High-K insulation film can be kept in a high state, a semiconductor device is disclosed that includes a silicon substrate, a gate electrode layer, and a gate insulation film between the silicon substrate and the gate electrode layer. The gate insulation film is a high relative permittivity (high-k) film being formed by performing a nitriding treatment on a mixture of a metal and silicon. The High-K film itself becomes a nitride so as to prevent SiO2 from being formed.
摘要翻译： 为了通过将高K绝缘膜的相对介电常数保持在高状态来提供具有良好质量的半导体器件，或者提供一种半导体器件的制造方法，其中高K绝缘膜的相对介电常数可以 保持在高状态，公开了在硅衬底和栅极电极层之间包括硅衬底，栅极电极层和栅极绝缘膜的半导体器件。 栅极绝缘膜是通过对金属和硅的混合物进行氮化处理而形成的高相对介电常数（高k）膜。 High-K膜本身成为氮化物，以防止形成SiO 2。
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公开(公告)号：US20060278909A1
公开(公告)日：2006-12-14
申请号：US10560706
申请日：2004-06-11
IPC分类号： H01L29/94
CPC分类号： H01L29/7851 , H01L21/823807 , H01L21/823821 , H01L21/82385 , H01L29/045
摘要： A MIS transistor, formed on a semiconductor substrate, assumed to comprise a semiconductor substrate (702, 910) comprising a projecting part (704, 910B) with at least two different crystal planes on the surface on a principal plane, a gate insulator (708, 920B) for covering at least a part of each of said at least two different crystal planes constituting the surface of the projecting part, a gate electrode (706, 930B), comprised on each of said at least two different crystal planes constituting the surface of the projecting part, which sandwiches the gate insulator with the said at least two different planes, and a single conductivity type diffusion region (710a, 710b, 910c, 910d) formed in the projecting part facing each of said at least two different crystal planes and individually formed on both sides of the gate electrode. Such a configuration allows control over increase in the element area and increase of channel width.
摘要翻译： 形成在半导体衬底上的MIS晶体管被认为包括半导体衬底（702,910），该半导体衬底包括在主平面上的表面上具有至少两个不同晶面的突出部分（704,910B），栅极绝缘体 708,920B），用于覆盖构成突出部分的表面的所述至少两个不同晶面的每一个的至少一部分;栅电极（706,930B），包括在所述至少两个不同晶面中的每一个上 构成突出部分的表面，其将栅极绝缘体与所述至少两个不同的平面夹住，并且形成在突出部分中的单个导电型扩散区域（710a，710b，910c，910d） 所述至少两个不同的晶面并且分别形成在所述栅电极的两侧。 这种配置允许控制元件面积的增加和通道宽度的增加。
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公开(公告)号：US20060138476A1
公开(公告)日：2006-06-29
申请号：US10560704
申请日：2004-06-11
IPC分类号： H01L29/76
CPC分类号： H01L29/7851 , H01L21/823807 , H01L21/82385 , H01L27/092 , H01L29/66795 , H03F3/343 , H03F3/45183 , H03F2200/372
摘要： A rectangular parallelepiped projecting portion 21 having a height of HB and a width of WB is formed on a silicon substrate, and a gate oxide film is formed on a part of the top surface and the side surface of the projecting portion 21. A source and a drain are formed on both sides of the gate electrode 26 to form a MOS transistor. The MOS transistor configures a DC amplifier. The DC amplifier includes a differential amplification circuit having MOS transistors 61 and 62, thereby realizing a high-gain DC amplifier.
摘要翻译： 在硅衬底上形成具有H B B高度和W B B的宽度的长方体的突出部分21，并且栅极氧化膜形成在 突出部分21的顶表面和侧表面。 源极和漏极形成在栅电极26的两侧以形成MOS晶体管。 MOS晶体管配置一个直流放大器。 DC放大器包括具有MOS晶体管61和62的差分放大电路，从而实现高增益DC放大器。
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公开(公告)号：US20060131553A1
公开(公告)日：2006-06-22
申请号：US10543166
申请日：2004-01-29
IPC分类号： H01L47/00
CPC分类号： H01L21/28167 , H01L21/02008 , H01L21/02027 , H01L21/02381 , H01L21/02428 , H01L21/02433 , H01L21/02532 , H01L21/02658 , H01L29/045
摘要： The present invention has been made in order to manufacture a silicon semiconductor substrate used for a semiconductor integrated circuit device, higher in carrier mobility, especially in electron mobility, which is a carrier of an n-type FET, on a {100} plane as a main surface, and provides a silicon semiconductor substrate and a method for manufacturing the same, wherein the conventional RCA cleaning is employed without the use of special cleaning and the surface of the substrate is planarized at an atomic level to thereby decrease the surface roughness thereof without the use of the radical oxidation. The present invention provides a silicon semiconductor substrate comprising: a {110} plane or a plane inclined from a {110} plane as a main surface of the substrate; and steps arranged at an atomic level along a orientation on the main surface.
摘要翻译： 本发明是为了制造用于半导体集成电路器件的硅半导体衬底，在{100}面作为载流子迁移率，尤其是作为n型FET的载流子的电子迁移率中，作为 主表面，并提供硅半导体衬底及其制造方法，其中采用常规的RCA清洗而不使用特殊的清洁，并且基板的表面在原子级平坦化，从而降低其表面粗糙度 而不使用自由基氧化。 本发明提供了一种硅半导体衬底，其包括：{110}面或从{110}面倾斜作为衬底的主表面的平面; 以及沿着主表面沿<110>方向布置在原子水平的台阶。
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公开(公告)号：US09875899B2
公开(公告)日：2018-01-23
申请号：US13582229
申请日：2011-03-02
申请人： Hiroshi Kambayashi , Katsunori Ueno , Takehiko Nomura , Yoshihiro Sato , Akinobu Teramoto , Tadahiro Ohmi
发明人： Hiroshi Kambayashi , Katsunori Ueno , Takehiko Nomura , Yoshihiro Sato , Akinobu Teramoto , Tadahiro Ohmi
CPC分类号： H01L21/28264 , C23C16/403 , C23C16/4488 , H01L21/02178 , H01L21/02277 , H01L29/2003 , H01L29/513 , H01L29/517 , H01L29/78
摘要： The semiconductor transistor according the present invention includes an active layer composed of a GaN-based semiconductor and a gate insulating film formed on the active layer. The gate insulating film has a first insulating film including one or more compounds selected from the group consisting of Al2O3, HfO2, ZrO2, La2O3, and Y2O3 formed on the active layer, and a second insulating film composed of SiO2 formed on the first insulating film.
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