公开(公告)号：US06864534B2

公开(公告)日：2005-03-08

申请号：US09930202

申请日：2001-08-16

Applicant: Takashi Ipposhi ,  Takuji Matsumoto

Inventor： Takashi Ipposhi ,  Takuji Matsumoto

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/336 ,  H01L21/762 ,  H01L23/544 ,  H01L29/04 ,  H01L29/786 ,  H01L27/01 ,  H01L29/00

CPC classification number: H01L23/544 ,  H01L21/76254 ,  H01L29/045 ,  H01L2223/54406 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/00

Abstract: To provide a semiconductor wafer having crystal orientations of a wafer for the support substrate and a wafer for the device formation shifted from each other, wherein two kinds of wafers having different crystal orientations in which a notch or an orientation flat is to be provided do not need to be prepared. One of two semiconductor wafers having a notch or an orientation flat provided in the same crystal orientation is set to be a wafer (1) for the support substrate and the other is set to be a wafer for the device formation. Both wafers are bonded with the notches or orientation flats shifted from each other (for example, a crystal orientation of the wafer for the device formation and the crystal orientation of the wafer (1) for the support substrate are set to the same direction). The wafer for the device formation is divided to obtain an SOI layer (3). A MOS transistor (TR1) or the like is formed on the SOI layer (3).

Abstract translation: 为了提供具有用于支撑基板的晶片的晶体取向和用于器件形成的晶片彼此偏移的半导体晶片，其中将提供具有不同晶体取向的两种晶片（其中将提供缺口或取向平面）不是 需要准备 将具有以相同晶体取向<110>提供的凹口或取向平面的两个半导体晶片中的一个设置为用于支撑衬底的晶片（1），另一个被设置为用于器件形成的晶片。 两个晶片与凹槽或取向平面彼此偏移（例如，用于器件形成的晶片的晶体取向<100>和用于支撑衬底的晶片（1）的晶体取向<110>被结合 朝同一个方向）。 用于器件形成的晶片被分割以获得SOI层（3）。 在SOI层（3）上形成MOS晶体管（TR1）等。

公开(公告)号：US06541841B2

公开(公告)日：2003-04-01

申请号：US10163613

申请日：2002-06-07

Applicant: Shigenobu Maeda ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

Inventor： Shigenobu Maeda ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

IPC: H01L2900

CPC classification number: H01L23/645 ,  H01L21/84 ,  H01L23/522 ,  H01L23/5227 ,  H01L27/0688 ,  H01L27/1203 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device with a spiral inductor is provided, which determines the area of an insulation layer to be provided in the surface of a wiring board thereunder. A trench isolation oxide film, which is a complete isolation oxide film including in part the structure of a partial isolation oxide film, is provided in a larger area of the surface of an SOI layer than that corresponding to the area of a spiral inductor. The trench isolation oxide film is comprised of a first portion having a first width and extending in a direction approximately perpendicular the surface of a buried oxide film, and a second portion having a second width smaller than the first width and being continuously formed under the first portion, extending approximately perpendicular to the surface of the buried oxide film. The trench isolation oxide film is provided such that a horizontal distance between each end surface of the second portion and a corresponding end surface of the spiral inductor makes a predetermined distance or more.

Abstract translation: 提供具有螺旋电感器的半导体器件，其确定要在其下面的布线板的表面中提供的绝缘层的面积。 在SOI层表面的与螺旋形电感器的面积相对应的面的大面积上，设置有作为部分隔离氧化膜的结构的完全隔离氧化膜的沟槽隔离氧化膜。 沟槽隔离氧化膜由具有第一宽度的第一部分和大致垂直于埋入氧化膜的表面的方向延伸的第一部分和具有小于第一宽度的第二宽度的第二部分构成，并且连续地形成在第一 部分，大致垂直于掩埋氧化膜的表面延伸。 沟槽隔离氧化膜被设置为使得第二部分的每个端表面与螺旋电感器的相应端面之间的水平距离达到预定距离或更大。

公开(公告)号：US06452249B1

公开(公告)日：2002-09-17

申请号：US09688812

申请日：2000-10-17

Applicant: Shigenobu Maeda ,  Yasuo Yamaguchi ,  Yuuichi Hirano ,  Takashi Ipposhi ,  Takuji Matsumoto

Inventor： Shigenobu Maeda ,  Yasuo Yamaguchi ,  Yuuichi Hirano ,  Takashi Ipposhi ,  Takuji Matsumoto

IPC: H01L2900

CPC classification number: H01L23/5227 ,  H01L21/28518 ,  H01L21/84 ,  H01L23/645 ,  H01L27/0688 ,  H01L27/08 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having an inductor is provided. In an RF circuit portion (RP), a region in an SOI layer (3) corresponding to a region in which a spiral inductor (SI) is provided is divided into a plurality of SOI regions (21) by a plurality of trench isolation oxide films (11). The trench isolation oxide films (11) are formed by filling trenches extending from the surface of the SOI layer (3) to the surface of a buried oxide film (2) with a silicon oxide film, and completely electrically isolate the SOI regions (21) from each other. The trench isolation oxide films (11) have a predetermined width and are shaped to extend substantially perpendicularly to the surface of the buried oxide film (2). The semiconductor device is capable of reducing electrostatically induced power dissipation and electromagnetically induced power dissipation, and preventing the structure and manufacturing steps thereof from becoming complicated.

Abstract translation: 提供具有电感器的半导体器件。 在RF电路部分（RP）中，与设置有螺旋电感器（SI）的区域对应的SOI层（3）中的区域被多个沟槽隔离氧化物（21）分成多个SOI区域 电影（11）。 沟槽隔离氧化膜（11）通过用氧化硅膜填充从SOI层（3）的表面延伸到掩埋氧化膜（2）的表面的沟槽而形成，并将SOI区域（21 ）彼此。 沟槽隔离氧化物膜（11）具有预定的宽度并且被成形为基本上垂直于掩埋氧化膜（2）的表面延伸。 半导体器件能够降低静电感应功率耗散和电磁感应功率消耗，并且防止其结构和制造步骤变得复杂。

公开(公告)号：US06426543B1

公开(公告)日：2002-07-30

申请号：US09717038

申请日：2000-11-22

Applicant: Shigenobu Maeda ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

Inventor： Shigenobu Maeda ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

IPC: H01L2900

CPC classification number: H01L23/645 ,  H01L21/84 ,  H01L23/522 ,  H01L23/5227 ,  H01L27/0688 ,  H01L27/1203 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device with a spiral inductor is provided, which determines the area of an insulation layer to be provided in the surface of a wiring board thereunder. A trench isolation oxide film, which is a complete isolation oxide film including in part the structure of a partial isolation oxide film, is provided in a larger area of the surface of an SOI layer than that corresponding to the area of a spiral inductor. The trench isolation oxide film includes a first portion having a first width and extending in a direction approximately perpendicular the surface of a buried oxide film, and a second portion having a second width smaller than the first width and being continuously formed under the first portion, extending approximately perpendicular to the surface of the buried oxide film. The trench isolation oxide film is provided such that a horizontal distance between each end surface of the second portion and a corresponding end surface of the spiral inductor makes a predetermined distance or more.

Abstract translation: 提供具有螺旋电感器的半导体器件，其确定要在其下面的布线板的表面中提供的绝缘层的面积。 在SOI层表面的与螺旋形电感器的面积相对应的面的大面积上，设置有作为部分隔离氧化膜的结构的完全隔离氧化膜的沟槽隔离氧化膜。 沟槽隔离氧化膜包括具有第一宽度并且在大致垂直于掩埋氧化膜的表面的方向上延伸的第一部分和具有小于第一宽度的第二宽度的第二部分并且连续地形成在第一部分下方， 大致垂直于埋入氧化膜的表面延伸。 沟槽隔离氧化膜被设置为使得第二部分的每个端表面与螺旋电感器的相应端面之间的水平距离达到预定距离或更大。

公开(公告)号：US06410973B1

公开(公告)日：2002-06-25

申请号：US09339388

申请日：1999-06-24

Applicant: Toshiaki Iwamatsu ,  Takashi Ipposhi

Inventor： Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC: H01L2902

Abstract: A semiconductor integrated circuit is formed by MESA isolation of a thin film silicon layer, in which transistor characteristics are free from influence depending on pattern density of transistor forming regions. The thin film silicon layer on an insulating substrate is isolated by MESA isolation, and element forming regions are formed. In the middle part of a large distance between adjacent element forming regions, a LOCOS oxide film is thickly formed, and an oxide film is buried between the LOCOS oxide film and the element forming regions contiguously at the same surface level so that there is no step-like level difference therebetween.

公开(公告)号：US06380089B1

公开(公告)日：2002-04-30

申请号：US09311360

申请日：1999-05-13

Applicant: Takashi Ipposhi ,  Toshiaki Iwamatsu

Inventor： Takashi Ipposhi ,  Toshiaki Iwamatsu

IPC: H01L21302

CPC classification number: H01L21/7624 ,  H01L21/30604 ,  H01L21/3065

Abstract: An SOI layer is thinned without a thermal oxidation process. An SOI substrate (10) is immersed in an etching bath filled with an NH3—H2O2—H2O solution to be isotropically etched. This produces a 100-mn thick SOI layer (3) with no crystal defect.

Abstract translation: SOI层在没有热氧化过程的情况下变薄。 将SOI衬底（10）浸入填充有NH 3 -H 2 O 2·H 2 O溶液的蚀刻浴中以进行各向同性蚀刻。 这产生了100nm厚的SOI层（3），没有晶体缺陷。

公开(公告)号：US06310377B1

公开(公告)日：2001-10-30

申请号：US09134896

申请日：1998-08-17

Applicant: Shigenobu Maeda ,  Yasuo Yamaguchi ,  Il Jung Kim ,  Yasuo Inoue ,  Shigeto Maegawa ,  Takashi Ipposhi

Inventor： Shigenobu Maeda ,  Yasuo Yamaguchi ,  Il Jung Kim ,  Yasuo Inoue ,  Shigeto Maegawa ,  Takashi Ipposhi

IPC: H01L2701

CPC classification number: H01L21/76202 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76291 ,  H01L27/11807 ,  H01L27/1203

Abstract: FS-isolated fields (10a, 10b). LOCOS-isolated fields (11c, 11d). FS-isolated fields (10e, 10f), LOCOS-isolated field (11g, 11h) and FS-isolated field (10i) are arranged in this order. Thus, a master layout can he provided, where SOI transistors having bodies to be supplied with fixed potential and those having bodies not to be supplied with fixed potential are mixed.

Abstract translation: FS隔离场（10a，10b）。 LOCOS隔离场（11c，11d）。 FS隔离场（10e，10f），LOCOS隔离场（11g，11h）和FS隔离场（10i）按此顺序排列。 因此，可以提供主布局，其中将具有被提供固定电位的主体和具有不具有固定电位的主体的SOI晶体管混合。

公开(公告)号：US06255146B1

公开(公告)日：2001-07-03

申请号：US09699461

申请日：2000-10-31

Applicant: Satoshi Shimizu ,  Shuichi Ueno ,  Shigenobu Maeda ,  Takashi Ipposhi

Inventor： Satoshi Shimizu ,  Shuichi Ueno ,  Shigenobu Maeda ,  Takashi Ipposhi

IPC: H01L2100

CPC classification number: H01L27/1108 ,  H01L27/1281 ,  H01L27/1285 ,  H01L29/66757 ,  H01L29/78624 ,  H01L29/78675 ,  H01L29/78678 ,  Y10S257/914

Abstract: According to a method of manufacturing a thin film transistor (TFT), amorphous silicon is formed by ion-implanting either silicon or nitrogen into a region of polysilicon while a region located at the sidewall of a gate electrode is selectively left using the stepped portion of the gate electrode. Then, a heat treatment is applied to convert the amorphous silicon into polysilicon with the remaining polysilicon as a seed crystal. As a result, polysilicon having crystal grains of great grain size can be formed in uniform. Thus, the electric characteristics of a TFT can be improved with no difference in the electric characteristics between each TFT.

Abstract translation: 根据制造薄膜晶体管（TFT）的方法，通过将硅或氮离子注入到多晶硅的区域中形成非晶硅，而位于栅电极的侧壁的区域选择性地使用步骤部分 栅电极。 然后，进行热处理以将非晶硅转化为多晶硅，剩余的多晶硅作为晶种。 结果，可以均匀地形成具有大晶粒尺寸的晶粒的多晶硅。 因此，可以提高TFT的电特性，并且每个TFT之间的电特性没有差异。

公开(公告)号：US06188085B1

公开(公告)日：2001-02-13

申请号：US09335691

申请日：1999-06-18

Applicant: Satoshi Shimizu ,  Shuichi Ueno ,  Shigenobu Maeda ,  Takashi Ipposhi

Inventor： Satoshi Shimizu ,  Shuichi Ueno ,  Shigenobu Maeda ,  Takashi Ipposhi

IPC: H01L29786

CPC classification number: H01L27/1108 ,  H01L27/1281 ,  H01L27/1285 ,  H01L29/66757 ,  H01L29/78624 ,  H01L29/78675 ,  H01L29/78678 ,  Y10S257/914

Abstract: According to a method of manufacturing a thin film transistor (TFT), amorphous silicon is formed by ion-implanting either silicon or nitrogen into a region of polysilicon while a region located at the sidewall of a gate electrode is selectively left using the stepped portion of the gate electrode. Then, a heat treatment is applied to convert the amorphous silicon into polysilicon with the remaining polysilicon as a seed crystal. As a result, polysilicon having crystal grains of great grain size can be formed in uniform. Thus, the electric characteristics of a TFT can be improved with no difference in the electric characteristics between each TFT.

公开(公告)号：US6124619A

公开(公告)日：2000-09-26

申请号：US877202

申请日：1997-06-17

Applicant: Shigenobu Maeda ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

Inventor： Shigenobu Maeda ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

IPC: H01L21/76 ,  H01L21/765 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L29/402 ,  H01L21/765 ,  H01L29/4232

Abstract: In order to improve isolation between an FS (field shielding) electrode and a gate electrode (6), upper and lower major surfaces of a polysilicon layer (35) forming a principal part of an FS electrode (5) are covered with nitride films (SiN films) (34, 36) respectively. Therefore, it is possible to inhibit portions in the vicinity of edge portions of the polysilicon layer (35) from being oxidized by an oxidant following oxidation for forming a gate insulating film (14). Thus, the polysilicon layer (35) is inhibited from deformation following oxidation, whereby the distance between an FS electrode (5) and a gate electrode (6) is sufficiently ensured. Consequently, isolation between the FS electrode (5) and the gate electrode (6) is improved.

Abstract translation: 为了改善FS（场屏蔽）电极和栅电极（6）之间的隔离，形成FS电极（5）的主要部分的多晶硅层（35）的上主表面和下主表面被氮化物膜（ SiN膜）（34,36）。 因此，可以抑制多晶硅层（35）的边缘部分附近的部分被形成栅极绝缘膜（14）的氧化后的氧化剂氧化。 因此，抑制氧化后的多晶硅层（35）变形，从而充分确保了FS电极（5）与栅电极（6）之间的距离。 因此，提高了FS电极（5）与栅电极（6）之间的隔离。