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    High-speed serial data signal transmitter driver circuitry
    71.
    发明申请
    High-speed serial data signal transmitter driver circuitry 审中-公开
    高速串行数据信号发射器驱动电路

    公开(公告)号：US20090154591A1

    公开(公告)日：2009-06-18

    申请号：US12002540

    申请日：2007-12-17

    申请人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Weiqi Ding

    发明人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Weiqi Ding

    IPC分类号： H04L27/00

    CPC分类号： H04L25/028

    摘要： Transmitter driver circuitry for outputting a high-speed serial data signal (e.g., in the range of about 10 gigabits per second or higher) includes H-tree driver circuitry having only a main driver stage and a post-tap driver stage. At least one transistor in the H-tree driver circuitry is constructed and connected to provide electrostatic discharge protection. PMOS and NMOS current sources are used for the H-tree driver circuitry to enhance power supply noise rejection.

    摘要翻译： 用于输出高速串行数据信号（例如，在大约10吉比特每秒或更高的范围内）的发射器驱动器电路包括仅具有主驱动器级和抽头后驱动级的H树驱动器电路。 H树驱动器电路中的至少一个晶体管被构造和连接以提供静电放电保护。 PMOS和NMOS电流源用于H-tree驱动器电路，以增强电源噪声抑制。

    High-speed serial data signal receiver circuitry
    72.
    发明申请
    High-speed serial data signal receiver circuitry 有权
    高速串行数据信号接收电路

    公开(公告)号：US20090154542A1

    公开(公告)日：2009-06-18

    申请号：US12002539

    申请日：2007-12-17

    申请人： Weiqi Ding ,  Mengchi Liu ,  Wilson Wong ,  Sergey Shumarayev

    发明人： Weiqi Ding ,  Mengchi Liu ,  Wilson Wong ,  Sergey Shumarayev

    IPC分类号： H03H7/30

    CPC分类号： H04L25/03885 ,  H04L7/0054 ,  H04L25/03019 ,  H04L25/03878

    摘要： Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gpbs and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g., 64 parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.

    摘要翻译： 用于接收高速串行数据信号（例如，具有在约10Gpbs及更高的范围内的比特率）的电路包括仅具有两个串联连接级的两级连续时间线性均衡器。 可以提供相位检测器电路用于接收均衡器的串行输出，并将该输出中的连续比特对转换为连续并行形式的位对。 可以提供进一步的解复用电路以将并行形式位对的连续组分解成最终并行位组，在位数（例如，64个并行位）方面可能相当大。 本发明的另一方面涉及用于从相对大的并行数据比特组相对于高速串行数据输出信号有效地进行反向的多路复用器电路。

    High-speed serial interface architecture for a programmable logic device
    73.
    发明授权
    High-speed serial interface architecture for a programmable logic device 有权
    用于可编程逻辑器件的高速串行接口架构

    公开(公告)号：US07460040B1

    公开(公告)日：2008-12-02

    申请号：US11754670

    申请日：2007-05-29

    申请人： Thungoc M. Tran ,  Yu Xu ,  Kwong-Wen Wei ,  Sergey Shumarayev

    发明人： Thungoc M. Tran ,  Yu Xu ,  Kwong-Wen Wei ,  Sergey Shumarayev

    IPC分类号： H03M9/00

    CPC分类号： H03M9/00 ,  H03K5/135 ,  H03K19/1774 ,  H03K19/17744

    摘要： A high-speed serial interface for a programmable logic device includes a plurality of features to handle the various issues that may arise with data rates over 1 Gbps and particularly over 1.25 Gbps. Those features may include dynamic phase alignment to control clock-data skew, data realignment (e.g., bit slip circuitry) to account for channel-to-channel skew, full-duplex serializer and deserializer, out-of-range frequency support for low frequencies, and a soft-CDR mode.

    摘要翻译： 用于可编程逻辑器件的高速串行接口包括多个特征，以处理在1Gbps，特别是超过1.25Gbps的数据速率下可能出现的各种问题。 这些特征可以包括动态相位对准以控制时钟数据偏移，数据重新对准（例如位移电路）以解决通道间通道偏移，全双工串行器和解串器，超低频率频率支持 ，和软CDR模式。

    Dynamic bias circuit
    74.
    发明授权
    Dynamic bias circuit 有权
    动态偏置电路

    公开(公告)号：US07358883B1

    公开(公告)日：2008-04-15

    申请号：US11470343

    申请日：2006-09-06

    申请人： Tin H. Lai ,  Wilson Wong ,  Sergey Shumarayev

    发明人： Tin H. Lai ,  Wilson Wong ,  Sergey Shumarayev

    IPC分类号： H03M1/66

    CPC分类号： G11C7/12 ,  G11C7/1045 ,  H03M1/662

    摘要： A bias circuit includes a digital to analog converter (D2A) generating an output representing a voltage level for tuning an analog signal. The D2A is coupled to a primary register frame that includes a plurality of register frames that are serially linked. The bias circuit includes a decoder also coupled to the primary register frame. An output enable logic module is also included. The output enable logic module determines when the primary register has a complete data set as the data is shifted into the primary register frame from a memory region that may be a ROM, RAM, soft IP of a PLD, an intelligent host or tester serial data input stream. A method for adjusting a signal through a bias circuit is also provided.

    摘要翻译： 偏置电路包括产生表示用于调谐模拟信号的电压电平的输出的数模转换器（D2A）。 D2A耦合到包括多个串行连接的寄存器帧的主寄存器帧。 偏置电路包括还耦合到主寄存器框架的解码器。 还包括一个输出使能逻辑模块。 输出使能逻辑模块确定主寄存器何时具有完整数据集，因为数据从可能是ROM，RAM，PLD的软IP，智能主机或测试仪串行数据的存储器区域移入主寄存器帧 输入流。 还提供了一种通过偏置电路调整信号的方法。

    Adjustable differential input and output drivers
    75.
    发明授权
    Adjustable differential input and output drivers 有权
    可调差分输入和输出驱动器

    公开(公告)号：US07245144B1

    公开(公告)日：2007-07-17

    申请号：US11169242

    申请日：2005-06-27

    申请人： Wilson Wong ,  Sergey Shumarayev

    发明人： Wilson Wong ,  Sergey Shumarayev

    IPC分类号： H03K17/16

    CPC分类号： H03K19/018564 ,  H03F3/45928 ,  H03F2203/45078 ,  H03F2203/45082 ,  H03F2203/45101 ,  H03F2203/45134 ,  H03F2203/45138 ,  H03F2203/45154 ,  H03F2203/45222 ,  H03F2203/45541 ,  H03F2203/45566 ,  H03F2203/45626 ,  H03F2203/45681 ,  H03F2203/45686

    摘要： Systems and methods are provided using common-mode-voltage bias circuitry to make common-mode-voltage adjustments to differential driver circuitry in integrated circuit differential communications links. Adjustable bias circuitry may be controlled using static and dynamic control signals. Dynamic control signals can be produced by core logic on a programmable logic device or other integrated circuit. Static control signals can be produced by programmable elements. Bias circuit adjustments made at one end of a differential link can be used to improve performance at either end of the link or can be used to improve power consumption or to balance power and performance considerations. The same integrated circuit design can be used in both AC-coupled and DC-coupled environments. The bias circuitry can be formed from an adjustable current source and adjustable resistor. The current source and adjustable resistors can be controlled by the same control signals.

    摘要翻译： 使用共模电压偏置电路提供系统和方法，以对集成电路差分通信链路中的差分驱动器电路进行共模电压调整。 可调节的偏置电路可以使用静态和动态控制信号来控制。 动态控制信号可以由可编程逻辑器件或其他集成电路上的核心逻辑产生。 静态控制信号可以由可编程元件产生。 差分链路一端进行的偏置电路调整可用于提高链路两端的性能，或者可用于提高功耗或平衡功率和性能考虑。 同样的集成电路设计可用于交流耦合和直流耦合环境。 偏置电路可以由可调电流源和可调电阻器形成。 电流源和可调电阻可由相同的控制信号控制。

    Programmable receiver equalization circuitry and methods
    76.
    发明申请
    Programmable receiver equalization circuitry and methods 有权
    可编程接收机均衡电路和方法

    公开(公告)号：US20070014344A1

    公开(公告)日：2007-01-18

    申请号：US11182658

    申请日：2005-07-14

    申请人： Simardeep Maangat ,  Sergey Shumarayev ,  Wilson Wong ,  ThuNgoc Tran

    发明人： Simardeep Maangat ,  Sergey Shumarayev ,  Wilson Wong ,  ThuNgoc Tran

    IPC分类号： H03H7/30

    CPC分类号： H04L25/03885 ,  H04B3/04 ,  H04L25/03019

    摘要： Data signals transmitted over transmission media suffer from attenuation caused by the transmission media. Equalization circuitry may be provided to compensate for attenuation caused by the transmission media. Equalization circuitry may include multiple stages arranged in series to allow the frequency responses of the stages to aggregate together. Each stage may be programmable to insert a zero, which causes the frequency response of the stage to increase in magnitude by 20 dB/decade. The frequency location of the zero may also be programmable to allow each stage to contribute a certain amount of gain for a specific frequency. Each stage may also be programmable to determine the location of poles for reduction of high frequency noise and cross-talk cancellation.

    摘要翻译： 通过传输介质传输的数据信号遭受由传输介质引起的衰减。 可以提供均衡电路以补偿由传输介质引起的衰减。 均衡电路可以包括串联布置的多个级，以允许级的频率响应聚合在一起。 每个级可以是可编程的，以插入一个零，这使得该级的频率响应在幅度上增加20dB /十倍。 零的频率位置也可以是可编程的，以允许每个级对特定频率贡献一定量的增益。 每个阶段也可以被编程以确定用于降低高频噪声和串扰取消的极点的位置。

    Programmable termination with DC voltage level control
    79.
    发明授权
    Programmable termination with DC voltage level control 有权
    具有直流电压电平控制的可编程终端

    公开(公告)号：US06980022B1

    公开(公告)日：2005-12-27

    申请号：US10946902

    申请日：2004-09-21

    申请人： Sergey Shumarayev ,  Thomas White

    发明人： Sergey Shumarayev ,  Thomas White

    IPC分类号： H04L25/02 ,  H03K19/0175

    CPC分类号： H04L25/0278 ,  H04L25/0272 ,  H04L25/0284 ,  H04L25/0296 ,  H04L25/0298

    摘要： Various embodiments for implementing circuits and systems with highly flexible interface circuitry that is capable of realizing programmable on-chip termination and DC level control. A number of techniques use existing I/O resources to implement programmable on-chip termination and DC level control that enable an integrated circuit to meet a variety of different high speed single-ended and differential I/O standards.

    摘要翻译： 用于实现具有高度灵活的接口电路的电路和系统的各种实施例，其能够实现可编程片上终止和DC电平控制。 许多技术使用现有的I / O资源实现可编程片上终止和DC电平控制，使集成电路能够满足各种不同的高速单端和差分I / O标准。