公开(公告)号：US07118997B2

公开(公告)日：2006-10-10

申请号：US10905977

申请日：2005-01-28

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III.

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III.

IPC分类号： H01L21/425

CPC分类号： H01L29/66545 ,  H01L21/0273 ,  H01L21/266 ,  H01L21/28035 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/6659

摘要： A method for implanting gate regions essentially without implanting regions of the semiconductor layer where source/drain regions will be later formed. The method includes the steps of (a) providing (i) a semiconductor layer, (ii) a gate dielectric layer on the semiconductor layer, (iii) a gate region on the gate dielectric layer, wherein the gate region is electrically insulated from the semiconductor layer by the gate dielectric layer; (b) forming a resist layer on the gate dielectric layer and the gate region; (c) removing a cap portion of the resist layer essentially directly above the gate region essentially without removing the remainder of the resist layer; and (d) implanting the gate region essentially without implanting the semiconductor layer.

摘要翻译： 一种注入栅极区域的方法，其基本上不注入将在其后形成源极/漏极区域的半导体层的区域。 该方法包括以下步骤：（i）在半导体层上提供（i）半导体层，（ii）栅极电介质层，（iii）栅极介电层上的栅极区域，其中栅极区域与 半导体层由栅介质层; （b）在栅介质层和栅极区上形成抗蚀剂层; （c）基本上直接在栅极区域上方去除抗蚀剂层的盖部分，而不去除抗蚀剂层的其余部分; 和（d）基本上不注入半导体层来注入栅极区域。

公开(公告)号：US07071047B1

公开(公告)日：2006-07-04

申请号：US10905980

申请日：2005-01-28

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： H01L21/336

CPC分类号： H01L29/0653 ,  B82Y10/00 ,  H01L21/28114 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76243 ,  H01L21/76267 ,  H01L21/76283 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78654 ,  H01L29/78684

摘要： Semiconductor structures and method of forming semiconductor structures. The semiconductor structures including nano-structures or fabricated using nano-structures. The method of forming semiconductor structures including generating nano-structures using a nano-mask and performing additional semiconductor processing steps using the nano-structures generated.

摘要翻译： 半导体结构和形成半导体结构的方法。 包括纳米结构或使用纳米结构制造的半导体结构。 形成半导体结构的方法包括使用纳米掩模生成纳米结构，并使用所生成的纳米结构进行附加的半导体加工步骤。

公开(公告)号：US06998204B2

公开(公告)日：2006-02-14

申请号：US10707009

申请日：2003-11-13

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Peter H. Mitchell ,  Larry A. Nesbit

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Peter H. Mitchell ,  Larry A. Nesbit

IPC分类号： G01F9/00

CPC分类号： G03F1/30 ,  G03F1/54 ,  G03F1/68

摘要： The invention provides a method of forming a phase shift mask and the resulting phase shift mask. The method forms a non-transparent film on a transparent substrate and patterns an etch stop layer on the non-transparent film. The invention patterns the non-transparent film using the etch stop layer to expose areas of the transparent substrate. Next, the invention forms a mask on the non-transparent film to protect selected areas of the transparent substrate and forms a phase shift oxide on exposed areas of the transparent substrate. Subsequently, the mask is removed and the phase shift oxide is polished down to the etch stop layer, after which the etch stop layer is removed.

摘要翻译： 本发明提供一种形成相移掩模的方法和所得到的相移掩模。 该方法在透明基板上形成不透明的薄膜，并在非透明薄膜上形成蚀刻停止层。 本发明使用蚀刻停止层来图案化非透明膜以暴露透明基底的区域。 接下来，本发明在非透明膜上形成掩模，以保护透明基板的选定区域，并在透明基板的曝光区域上形成相移氧化物。 随后，去除掩模并将相移氧化物抛光到蚀刻停止层，之后去除蚀刻停止层。

公开(公告)号：US06867143B1

公开(公告)日：2005-03-15

申请号：US09599783

申请日：2000-06-22

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H-L. Ma

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H-L. Ma

IPC分类号： C23F4/00 ,  C23G1/00 ,  H01L21/302 ,  H01L21/308 ,  H01L21/3213

CPC分类号： H01L21/3081 ,  C23F4/00 ,  C23G1/00 ,  H01L21/3086 ,  H01L21/32134

摘要： An etching process using germanium hard mask (25) includes forming a dielectric layer (15) over a major surface (11) of a semiconductor substrate (10) and depositing a metallic germanium layer (22) over the dielectric layer (15). The metallic germanium layer (22) is patterned through a photo resist (24) to form the germanium hard mask (25). The dielectric layer (15) is selectively etched through the germanium hard mask (25) to form a dielectric hard mask (35), through which the semiconductor substrate (10) is subsequently etched. After forming the dielectric hard mask (35), the germanium hard mask (25) is stripped away by oxidizing the metallic germanium hard mask (25) to transform it into a layer (27) of germanium oxide and rinsing the semiconductor substrate (10) in water to remove the germanium oxide layer (27). Preferably, the germanium hard mask (25) is removed before etching the semiconductor substrate (10).

摘要翻译： 使用锗硬掩模（25）的蚀刻工艺包括在半导体衬底（10）的主表面（11）上形成电介质层（15），并在电介质层（15）上沉积金属锗层（22）。 通过光致抗蚀剂（24）将金属锗层（22）图案化以形成锗硬掩模（25）。 通过锗硬掩模（25）选择性地蚀刻电介质层（15）以形成电介质硬掩模（35），随后蚀刻半导体衬底（10）。 在形成电介质硬掩模（35）之后，通过氧化金属锗硬掩模（25）将锗硬掩模（25）剥离，将其转化成氧化锗层（27）并冲洗半导体衬底（10）， 在水中以除去氧化锗层（27）。 优选地，在蚀刻半导体衬底（10）之前去除锗硬掩模（25）。

公开(公告)号：US06531724B1

公开(公告)日：2003-03-11

申请号：US09686740

申请日：2000-10-10

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

IPC分类号： H01L29772

CPC分类号： H01L21/76897 ,  H01L21/76888 ,  H01L21/76895

摘要： A method for forming a gate conductor cap in a transistor comprises the steps of: a) forming a polysilicon gate conductor; b) doping the polysilicon gate; c) doping diffusion areas; and d) capping the gate conductor by a nitridation method chosen from among selective nitride deposition and selective surface nitridation. The resulting transistor may comprise a capped gate conductor and borderless diffusion contacts, wherein the capping occurred by a nitridation method chosen from among selective nitride deposition and selective surface nitridation and wherein a portion of the gate conductor is masked during the nitridation method to leave open a contact area for a local interconnect or a gate contact.

摘要翻译： 一种用于在晶体管中形成栅极导体帽的方法，包括以下步骤：a）形成多晶硅栅极导体; b）掺杂多晶硅栅极; c）掺杂扩散区域; 以及d）通过从选择性氮化物沉积和选择性表面氮化中选择的氮化方法来封盖栅极导体。 所得到的晶体管可以包括封盖栅极导体和无边界扩散接触，其中通过选择性氮化物沉积和选择性表面氮化中选择的氮化方法发生封盖，并且其中在氮化方法期间掩模一部分栅极导体以留下开口 接触区域用于局部互连或门接触。

公开(公告)号：US06221704B1

公开(公告)日：2001-04-24

申请号：US09089650

申请日：1998-06-03

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  James S. Nakos ,  Paul A. Rabidoux

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  James S. Nakos ,  Paul A. Rabidoux

IPC分类号： H01L2144

CPC分类号： H01L21/76897 ,  H01L21/28123 ,  H01L21/823842 ,  H01L29/66575

摘要： Semiconductor devices are fabricated by providing a substrate; forming isolation regions in the substrate; forming a first insulating layer on the isolation regions and the substrate; forming a conductive-forming layer on the first insulating layer; forming a second insulating layer on the conductive layer; forming a resist layer on the second insulating layer; forming an opening through the resist down to the second insulating layer located vertically between the isolation region; removing the second insulating layer beneath the opening down to the conductive-forming layer; depositing a conductive material through the opening over the conductive layer; planarizing the second insulating layer and the conductive material; removing the second insulating layer, the conductive-forming layer and the first insulating layer except beneath the conductive material; and forming source/drain regions in the substrate; or by providing a substrate; forming isolation regions in the substrate; forming a first insulating layer on the isolation regions and the substrate; forming a first conductive-forming layer on the first insulating layer; forming a second conductive layer on the first conductive-forming layer; forming a second insulating layer on the second conductive layer; forming a resist layer on the second insulating layer; forming an opening through the resist down to the second insulating layer located vertically between the isolation region; removing the second insulating layer beneath the opening down to the second conductive layer; depositing a third insulating material through the opening over the conductive layer; planarizing the second insulating layer and the third insulating material; removing the second insulating layer, the first conductive-forming layer and second conductive layer and the first insulating layer except beneath the third insulating material; and forming source/drain regions in the substrate.

公开(公告)号：US07932549B2

公开(公告)日：2011-04-26

申请号：US10596022

申请日：2003-12-18

申请人： Steven J. Holmes ,  Toshiharu Furukawa ,  Mark C. Hakey ,  David V. Horak ,  Charles W. Koburger, III ,  Larry A. Nesbit

发明人： Steven J. Holmes ,  Toshiharu Furukawa ,  Mark C. Hakey ,  David V. Horak ,  Charles W. Koburger, III ,  Larry A. Nesbit

IPC分类号： H01L27/108

CPC分类号： H01L27/10864 ,  B82Y10/00 ,  H01L27/10861 ,  Y10S977/936 ,  Y10S977/943 ,  Y10S977/948

摘要： A trench-type storage device includes a trench in a substrate (100), with bundles of carbon nanotubes (202) lining the trench and a trench conductor (300) filling the trench. A trench dielectric (200) may be formed between the carbon nanotubes and the sidewall of the trench. The bundles of carbon nanotubes form an open cylinder structure lining the trench. The device is formed by providing a carbon nanotube catalyst structure on the substrate and patterning the trench in the substrate; the carbon nanotubes are then grown down into the trench to line the trench with the carbon nanotube bundles, after which the trench is filled with the trench conductor.

摘要翻译： 沟槽式存储装置包括在衬底（100）中的沟槽，具有衬在沟槽上的碳纳米管（202）的束和填充沟槽的沟槽导体（300）。 可以在碳纳米管和沟槽的侧壁之间形成沟槽电介质（200）。 碳纳米管束形成在沟槽内衬的开放圆筒结构。 该器件通过在衬底上提供碳纳米管催化剂结构并对衬底中的沟槽进行图案化而形成; 然后将碳纳米管向下生长到沟槽中以与碳纳米管束对准沟槽，然后用沟槽导体填充沟槽。

公开(公告)号：US07889317B2

公开(公告)日：2011-02-15

申请号：US12051572

申请日：2008-03-19

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Peter H. Mitchell

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Peter H. Mitchell

IPC分类号： G03B27/42

CPC分类号： G03F7/70341

摘要： An immersion lithography apparatus and method, and a lithographic optical column structure are disclosed for conducting immersion lithography with at least the projection optics of the optical system and the wafer in different fluids at the same pressure. In particular, an immersion lithography apparatus is provided in which a supercritical fluid is introduced about the wafer, and another fluid, e.g., an inert gas, is introduced to at least the projection optics of the optical system at the same pressure to alleviate the need for a special lens. In addition, the invention includes an immersion lithography apparatus including a chamber filled with a supercritical immersion fluid and enclosing a wafer to be exposed and at least a projection optic component of the optical system.

摘要翻译： 公开了一种浸没式光刻设备和方法以及平版印刷光学柱结构，用于在相同压力下用不同流体中的光学系统和晶片的至少投影光学器件进行浸没光刻。 特别地，提供了一种浸没式光刻设备，其中超临界流体被引入晶片周围，并且另一种流体（例如惰性气体）在相同的压力下被引入光学系统的至少投影光学器件以减轻需要 用于特殊镜头。 此外，本发明包括浸没式光刻设备，其包括填充有超临界浸没流体的腔室并且封装要暴露的晶片和至少光学系统的投影光学部件。

公开(公告)号：US07771604B2

公开(公告)日：2010-08-10

申请号：US10711758

申请日：2004-10-04

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338

摘要： A combined wide-image and loop-cutter pattern is provided for both cutting and forming a wide-image section to a hard mask on a substrate formed by sidewall imaging techniques in a reduced number of photolithographic steps. A single mask is formed which provides a wide mask section while additionally providing a mask to protect the critical edges of an underlying hard mask during hard mask etching. After the hard mask is cut into sections, the protective portions of the follow-on mask are removed to expose the critical edges of the underlying hard mask while maintaining shapes necessary for defining wide-image sections. Thus, the hard mask cutting, hard mask critical edge protecting, and large area mask may be formed in a reduced number of steps.

摘要翻译： 提供了组合的宽图像和环形切割器图案，用于在通过减少数量的光刻步骤的侧壁成像技术形成的基板上切割和形成宽图像部分到硬掩模。 形成单个掩模，其提供宽掩模部分，同时另外提供掩模以在硬掩模蚀刻期间保护下面的硬掩模的临界边缘。 在将硬掩模切割成部分之后，除去后续掩模的保护部分以暴露下面的硬掩模的临界边缘，​​同时保持限定宽图像部分所需的形状。 因此，可以以减少的步数形成硬掩模切割，硬掩模临界边缘保护和大面积掩模。

公开(公告)号：US07648819B2

公开(公告)日：2010-01-19

申请号：US12045290

申请日：2008-03-10

申请人： Steven J. Holmes ,  Mark C. Hakey ,  Toshiharu Furukawa ,  David V. Horak

发明人： Steven J. Holmes ,  Mark C. Hakey ,  Toshiharu Furukawa ,  David V. Horak

IPC分类号： G03F7/20

CPC分类号： G03F7/70341 ,  G03F7/70925

摘要： A method and apparatus for reduction and prevention of residue formation and removal of residues formed in an immersion lithography tool. The apparatus including incorporation of a cleaning mechanism within the immersion head of an immersion lithographic system or including a cleaning mechanism in a cleaning station of an immersion lithographic system.

摘要翻译： 一种用于减少和防止残留物形成和去除在浸没式光刻工具中形成的残留物的方法和装置。 该设备包括在浸没式光刻系统的浸没头部内并入清洁机构，或者在浸没式光刻系统的清洁站中包括清洁机构。