-
公开(公告)号:US09147612B2
公开(公告)日:2015-09-29
申请号:US14088445
申请日:2013-11-25
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Po-Cheng Huang , I-Ming Tseng , Yu-Ting Li , Chun-Hsiung Wang , Wu-Sian Sie , Yi-Liang Liu , Chia-Lin Hsu , Po-Chao Tsao , Chien-Ting Lin , Shih-Fang Tzou
IPC: H01L21/338 , H01L21/8234 , H01L21/265
CPC classification number: H01L21/823431 , H01L21/265 , H01L21/3086 , H01L29/6681
Abstract: The present invention provides a manufacturing method for forming a semiconductor structure, in which first, a substrate is provided, a hard mask is disposed on the substrate, the hard mask is then patterned to form a plurality of fin hard masks and a plurality of dummy fin hard masks, afterwards, a pattern transferring process is performed, to transfer the patterns of the fin hard masks and the fin hard masks into the substrate, so as to form a plurality of fin groups and a plurality of dummy fins. Each dummy fin is disposed on the end side of one fin group, and a fin cut process is performed, to remove each dummy fin.
Abstract translation: 本发明提供一种用于形成半导体结构的制造方法,其中首先设置基板,在基板上设置硬掩模,然后将硬掩模图案化以形成多个散热片硬掩模和多个虚拟 翅片硬掩模,然后进行图案转印处理,将翅片硬掩模和翅片硬掩模的图案转移到基板中,以形成多个翅片组和多个虚拟翅片。 每个假翅片设置在一个翅片组的端侧,并进行翅片切割处理,以去除每个假翅片。
-
公开(公告)号:US20150064929A1
公开(公告)日:2015-03-05
申请号:US14018447
申请日:2013-09-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: I-Ming Tseng , Shih-Hung Tsai , Rai-Min Huang , Yu-Ting Lin , Chien-Ting Lin , Shih-Fang Tzou
IPC: H01L21/02
CPC classification number: H01L29/66795 , H01L21/02164 , H01L21/02233 , H01L21/02271 , H01L21/02337 , H01L21/76224
Abstract: A method of gap filling includes providing a substrate having a plurality of gaps formed therein. Then, an in-situ steam generation oxidation is performed to form an oxide liner on the substrate. The oxide liner is formed to cover surfaces of the gaps. Subsequently, a high aspect ratio process is performed to form an oxide protecting layer on the oxide liner. After forming the oxide protecting layer, a flowable chemical vapor deposition is performed to form an oxide filling on the oxide protecting layer. More important, the gaps are filled up with the oxide filling layer.
Abstract translation: 间隙填充的方法包括提供其中形成有多个间隙的基板。 然后,进行原位蒸汽发生氧化,以在衬底上形成氧化物衬垫。 形成氧化物衬垫以覆盖间隙的表面。 随后,进行高纵横比处理以在氧化物衬垫上形成氧化物保护层。 在形成氧化物保护层之后,进行可流动的化学气相沉积以在氧化物保护层上形成填充氧化物。 更重要的是,间隙填充有氧化物填充层。
-
73.
公开(公告)号:US20150014808A1
公开(公告)日:2015-01-15
申请号:US13939204
申请日:2013-07-11
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Shih-Hung Tsai , Rai-Min Huang , I-Ming Tseng , Yu-Ting Lin , Chien-Ting Lin
IPC: H01L21/762 , H01L21/311 , H01L29/06
CPC classification number: H01L21/76224 , H01L21/02236 , H01L21/3065 , H01L21/3086 , H01L29/66818 , H01L29/7853
Abstract: A fabrication method for a semiconductor structure at least includes the following steps. First, a pattern mask with a predetermined layout pattern is formed on a substrate. The layout pattern is then transferred to the underneath substrate so as to form at least a fin-shaped structure in the substrate. Subsequently, a shallow trench isolation structure is formed around the fin-shaped structure. Afterwards, a steam oxidation process is carried out to oxidize the fin-shaped structure protruding from the shallow trench isolation and to form an oxide layer on its surface. Finally, the oxide layer is removed completely.
Abstract translation: 半导体结构的制造方法至少包括以下步骤。 首先,在基板上形成具有预定布局图案的图案掩模。 然后将布局图案转移到基底下方,以在基底中形成至少一个鳍状结构。 随后,在鳍状结构周围形成浅沟槽隔离结构。 之后,进行蒸汽氧化处理,使从浅沟槽隔离突出的鳍状结构氧化,并在其表面形成氧化物层。 最后,氧化层被完全去除。
-
公开(公告)号:US20250107454A1
公开(公告)日:2025-03-27
申请号:US18976359
申请日:2024-12-11
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Ying-Cheng Liu , Yi-An Shih , Yi-Hui Lee , Chen-Yi Weng , Chin-Yang Hsieh , I-Ming Tseng , Jing-Yin Jhang , Yu-Ping Wang
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on a first sidewall of the MTJ, and a second spacer on a second sidewall of the MTJ. Preferably, the first spacer and the second spacer are asymmetric, the first spacer and the second spacer have different heights, and a top surface of the MTJ includes a reverse V-shape.
-
公开(公告)号:US12262647B2
公开(公告)日:2025-03-25
申请号:US18592553
申请日:2024-03-01
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Chen-Yi Weng , Yi-Wei Tseng , Chin-Yang Hsieh , Jing-Yin Jhang , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Yu-Ping Wang
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.
-
公开(公告)号:US12133474B2
公开(公告)日:2024-10-29
申请号:US18373295
申请日:2023-09-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , Jing-Yin Jhang , I-Ming Tseng , Yu-Ping Wang , Chien-Ting Lin , Kun-Chen Ho , Yi-Syun Chou , Chang-Min Li , Yi-Wei Tseng , Yu-Tsung Lai , Jun Xie
Abstract: A method of fabricating magnetoresistive random access memory, including providing a substrate, forming a bottom electrode layer, a magnetic tunnel junction stack, a top electrode layer and a hard mask layer sequentially on the substrate, wherein a material of the top electrode layer is titanium nitride, a material of the hard mask layer is tantalum or tantalum nitride, and a percentage of nitrogen in the titanium nitride gradually decreases from a top surface of top electrode layer to a bottom surface of top electrode layer, and patterning the bottom electrode layer, the magnetic tunnel junction stack, the top electrode layer and the hard mask layer into multiple magnetoresistive random access memory cells.
-
公开(公告)号:US20240268124A1
公开(公告)日:2024-08-08
申请号:US18636306
申请日:2024-04-16
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Jing-Yin Jhang , Chien-Ting Lin
CPC classification number: H10B61/00 , G11C11/161 , H10B61/10 , H10N50/01 , H10N50/80
Abstract: A semiconductor structure includes a substrate, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and filling the spaces between the memory stack structures, a first interconnecting structure through the second dielectric layer, wherein a top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures, a third dielectric layer on the second dielectric layer, and a plurality of second interconnecting structures through the third dielectric layer, the second dielectric layer and the insulating layer on the top surfaces of the memory stack structures to contact the top surfaces of the memory stack structures.
-
公开(公告)号:US12029044B2
公开(公告)日:2024-07-02
申请号:US18127651
申请日:2023-03-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Jing-Yin Jhang , Chien-Ting Lin
CPC classification number: H10B61/00 , G11C11/161 , H10B61/10 , H10N50/01 , H10N50/80
Abstract: A semiconductor structure includes a substrate having a memory device region and a logic device region, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer on the memory device region, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and completely filling the spaces between the memory stack structures, and a first interconnecting structure formed in the second dielectric layer on the logic device region. A top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures.
-
公开(公告)号:US20230238043A1
公开(公告)日:2023-07-27
申请号:US18127651
申请日:2023-03-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Jing-Yin Jhang , Chien-Ting Lin
CPC classification number: G11C11/161 , H10B61/00 , H10B61/10 , H10N50/01 , H10N50/80
Abstract: A semiconductor structure includes a substrate having a memory device region and a logic device region, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer on the memory device region, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and completely filling the spaces between the memory stack structures, and a first interconnecting structure formed in the second dielectric layer on the logic device region. A top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures.
-
公开(公告)号:US11646069B2
公开(公告)日:2023-05-09
申请号:US17460348
申请日:2021-08-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Jing-Yin Jhang , Chien-Ting Lin
CPC classification number: G11C11/161 , H01L27/222 , H01L27/224 , H01L43/02 , H01L43/12
Abstract: A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.
-
-
-
-
-
-
-
-
-