公开(公告)号：US07033518B2

公开(公告)日：2006-04-25

申请号：US10602968

申请日：2003-06-24

申请人： Hui Ou Yang ,  Miao-Ju Hsu ,  Chao-Cheng Chen ,  Hun-Jan Tao

发明人： Hui Ou Yang ,  Miao-Ju Hsu ,  Chao-Cheng Chen ,  Hun-Jan Tao

IPC分类号： H01L21/00

CPC分类号： H01L21/31116 ,  H01J37/32935 ,  H01L22/26

摘要： A method of etching multi-layer films, the method including: (1) etching a plurality of layers according to etching parameters, (2) determining a plurality of optical characteristics each associated with one of the plurality of layers and determined during the etching of the associated one of the plurality of layers, and (3) determining dynamic etch progressions each based on one of the plurality of optical characteristics that is associated with a particular one of the plurality of layers undergoing the etching.

摘要翻译： 一种蚀刻多层膜的方法，所述方法包括：（1）根据蚀刻参数蚀刻多个层，（2）确定多个光学特性，每个光学特性与所述多个层之一相关联并且在蚀刻期间确定 所述多个层中的相关联的一个层，以及（3）基于所述多个光学特性之一确定动态蚀刻进展，所述多个光学特性与经历所述蚀刻的所述多个层中的特定一个层相关联。

公开(公告)号：US20050136678A1

公开(公告)日：2005-06-23

申请号：US10743979

申请日：2003-12-22

申请人： Chun-Li Chou ,  Yih-Ann Lin ,  Yi-Chen Huang ,  Chao-Cheng Chen ,  Hun-Jan Tao

发明人： Chun-Li Chou ,  Yih-Ann Lin ,  Yi-Chen Huang ,  Chao-Cheng Chen ,  Hun-Jan Tao

IPC分类号： H01L21/02 ,  H01L21/306 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/02071 ,  H01L21/02063 ,  H01L21/76807

摘要： A method for cleaning semiconductor substrates includes a DI water clean operation that uses a spin speed no greater than 350 rpm. The cleaning method may include additional cleaning operations such as an organic clean, an aqueous chemical clean or a DI water/ozone clean. The cleaning method may be used to clean substrates after the conclusion of an etching procedure which exposes a single film between a Cu-containing conductive material and the environment. The spin speed of the DI water clean operation prevents copper corrosion due to breakdown of the film that separates the Cu-containing conductive material from the environment.

摘要翻译： 用于清洁半导体衬底的方法包括使用不大于350rpm的旋转速度的去离子水清洁操作。 清洁方法可以包括附加的清洁操作，例如有机清洁剂，水性化学清洁剂或去离子水/臭氧清洁剂。 在完成了在含Cu导电材料和环境之间暴露单个膜的蚀刻过程结束之前，清洁方法可用于清洁衬底。 去离子水清洁操作的旋转速度可防止由于将含Cu导电材料与环境分离的膜破裂导致铜腐蚀。

公开(公告)号：US06790770B2

公开(公告)日：2004-09-14

申请号：US10035690

申请日：2001-11-08

申请人： Chao-Cheng Chen ,  Jen-Cheng Liu ,  Jyu-Horng Shieh

发明人： Chao-Cheng Chen ,  Jen-Cheng Liu ,  Jyu-Horng Shieh

IPC分类号： H01L214763

CPC分类号： H01L21/76808

摘要： A method if provided for improving a photolithographic patterning process in a dual damascene process by forming a resinous plug in a via opening to prevent out diffusion of nitrogen containing species from a low-k IMD layer in subsequent lithographic patterning and RIE etching processes to form a trench opening formed substantially over the via opening.

摘要翻译： 如果提供用于通过在通孔开口中形成树脂塞以改善来自低k IMD层的含氮物质的扩散的方法，以在随后的平版印刷图案化和RIE蚀刻工艺中形成二维镶嵌工艺中的光刻图案化方法 沟槽开口基本上形成在通孔开口上方。

公开(公告)号：US06323121B1

公开(公告)日：2001-11-27

申请号：US09570018

申请日：2000-05-12

申请人： Jen-Cheng Liu ,  Chao-Cheng Chen ,  Li-Chih Chao ,  Chia-Shiung Tsai ,  Ming-Huei Lui

发明人： Jen-Cheng Liu ,  Chao-Cheng Chen ,  Li-Chih Chao ,  Chia-Shiung Tsai ,  Ming-Huei Lui

IPC分类号： H01L214763

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76807

摘要： A method is described for cleaning freshly etched dual damascene via openings and preparing them for copper fill without damage or contamination of exposed organic or other porous low-k insulative layers. The method is entirely dry and does not expose the porous materials to contamination from moisture or solvents. The method is effective for removing all traces of residual polymer deposits from an in-process substrate wafers after via or damascene trench etching. The method employs an in-situ three-step treatment comprising a first step of exposing the electrically biased substrate wafer to a O2/N2 ashing plasma to remove photoresist and polymers, a second step immediately following the first step of remove silicon nitride etch stop layers, and a final step of treating the wafer with H2/N2 to remove copper polymer deposits formed during nitride removal. The H2/N2 plasma is capable of removing the difficult polymer residues which are otherwise only removable by wet stripping procedures. The H2/N2 plasma is not harmful to exposed porous low-k dielectric layers as well as copper metallurgy.

摘要翻译： 描述了一种用于通过开口清洁新鲜蚀刻的双镶嵌件的方法，并且它们用于铜填充而不损坏或污染暴露的有机或其它多孔低k绝缘层。 该方法是完全干燥的，并且不会使多孔材料暴露于水分或溶剂的污染物中。 该方法对于在通孔或镶嵌沟槽蚀刻之后从工艺衬底晶片去除残余聚合物沉积物的所有迹线是有效的。 该方法采用原位三步处理，其包括将电偏置的衬底晶片暴露于O 2 / N 2灰分等离子体以去除光致抗蚀剂和聚合物的第一步骤，紧接着在去除氮化硅蚀刻停止层的第一步骤之后的第二步骤 ，以及用H2 / N2处理晶片以除去在氮化物除去期间形成的铜聚合物沉积物的最后步骤。 H 2 / N 2等离子体能够去除困难的聚合物残余物，否则其仅可通过湿式剥离方法除去。 H2 / N2等离子体对暴露的多孔低k电介质层以及铜冶金无害。

公开(公告)号：US6133145A

公开(公告)日：2000-10-17

申请号：US169434

申请日：1998-10-09

申请人： Chao-Cheng Chen

发明人： Chao-Cheng Chen

IPC分类号： H01L21/027 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/32139 ,  H01L21/0273 ,  H01L21/76838

摘要： A process for fabricating an aluminum based interconnect structure, using a plasma treated photoresist shape as an etch mask, has been developed. The process features treating a photoresist shape, to be used as an etch mask during RIE patterning procedures, in a nitrogen containing plasma. The plasma nitrogen treated photoresist shape is eroded at a decreased rate, when compared to counterpart non-treated photoresist shapes, during the RIE procedure used to fabricate the aluminum based interconnect structure. The increased etch rate ratio, between layers used for the interconnect structure, and the plasma treated photoresist shape, allows thinner photoresist shapes to be used, and therefore allows narrower lines and spaces to be achieved.

摘要翻译： 已经开发了使用等离子体处理的光致抗蚀剂形状作为蚀刻掩模来制造铝基互连结构的方法。 该方法的特征是在含氮等离子体中处理光刻胶形状，以在RIE图案化步骤期间用作蚀刻掩模。 在用于制造铝基互连结构的RIE程序期间，与对照未处理的光致抗蚀剂形状相比，等离子体氮处理的光致抗蚀剂形状以降低的速率被侵蚀。 用于互连结构的层之间的增加的蚀刻速率比和等离子体处理的光致抗蚀剂形状允许使用更薄的光致抗蚀剂形状，因此允许实现更窄的线和空间。

公开(公告)号：US6043163A

公开(公告)日：2000-03-28

申请号：US999233

申请日：1997-12-29

申请人： Chia-Shiung Tsai ,  Chao-Cheng Chen ,  Hun-Jan Tao

发明人： Chia-Shiung Tsai ,  Chao-Cheng Chen ,  Hun-Jan Tao

IPC分类号： H01L21/3213 ,  H01L21/00 ,  H01L21/3065

CPC分类号： H01L21/32136

摘要： A new method of etching metal lines using HCl in the overetch step to prevent undercutting of the metal lines is described. Semiconductor device structures are provided in and on a semiconductor substrate. The semiconductor device structures are covered with an insulating layer. A barrier metal layer is deposited overlying the insulating layer. A metal layer is deposited overlying the barrier metal layer. A hard mask layer is deposited overlying the metal layer. The hard mask layer is covered with a layer of photoresist which is exposed, developed, and patterned to form the desired photoresist mask. The hard mask layer is etched away where it is not covered by the photoresist mask leaving a patterned hard mask. The metal layer is etched away where it is not covered by the patterned hard mask to form the metal lines. Overetching is performed to remove the barrier layer where it is not covered by the hard mask wherein HCl gas is one of the etchant gases used in the overetching whereby hydrogen ions from the HCl gas react with the metal layer and the barrier metal layer to form a passivation layer on the sidewalls of the metal lines thereby preventing undercutting of the metal lines resulting in metal lines having a vertical profile. The photoresist mask is removed and fabrication of the integrated circuit device is completed.

摘要翻译： 描述了在过蚀刻步骤中使用HCl蚀刻金属线以防止金属线的底切的新方法。 半导体器件结构设置在半导体衬底中和半导体衬底上。 半导体器件结构被绝缘层覆盖。 覆盖在绝缘层上的阻挡金属层被沉积​​。 沉积在阻挡金属层上的金属层。 覆盖金属层的硬掩模层被沉积。 硬掩模层被一层光致抗蚀剂覆盖，该层被曝光，显影和图案化以形成所需的光致抗蚀剂掩模。 将硬掩模层蚀刻掉，其中未被光致抗蚀剂掩模覆盖，留下图案化的硬掩模。 金属层被蚀刻掉，其中未被图案化的硬掩模覆盖以形成金属线。 进行过蚀刻以去除其未被硬掩模覆盖的阻挡层，其中HCl气体是用于过蚀刻中的蚀刻剂气体之一，其中来自HCl气体的氢离子与金属层和阻挡金属层反应形成 钝化层，从而防止金属线的底切，导致具有垂直轮廓的金属线。 去除光致抗蚀剂掩模并完成集成电路器件的制造。

公开(公告)号：US5989784A

公开(公告)日：1999-11-23

申请号：US55463

申请日：1998-04-06

申请人： Yu-Hua Lee ,  Cheng-Ming Wu ,  Chao-Cheng Chen

发明人： Yu-Hua Lee ,  Cheng-Ming Wu ,  Chao-Cheng Chen

IPC分类号： H01L21/768 ,  H01L23/525 ,  G03F7/40 ,  B44C1/22 ,  C03C15/00 ,  C25F3/00

CPC分类号： H01L23/5258 ,  H01L21/76802 ,  H01L2924/0002

摘要： A method of forming an etch stop layer 40 above a fuse 16 in a fuse opening (or window) 92 using a specialized 2 stage etch process. The invention has two important features: First, the etch stop layer 40 is formed from a polysilicon layer (P2 or P4) that is used to fabricate semiconductor devices on a substrate. The etch stop layer 40 is preferably formed of polysilicon layer to is used to from a contact to the substrate 10 (P2) or to form part of a capacitor (P4). Second, a specialized two stage etch process is used where the second stage etches the etch stop layer 40 while simultaneously forming a passivation layer 114 over a metal pad 85. The method comprises: forming fuses 16 over said isolation regions 10 over the fuse area 15; forming a first dielectric layer 30 overlying the fuses 16; forming an etch stop layer 40 over the first dielectric layer 30; forming an insulating layer 43 over the etch stop layer; forming a fuse opening 92 in the insulating layer 43 by etching, in a first etch stage, thorough fuse photoresist openings 90A and stopping the first etch stage on the etch stop layer 40; and etching though the etch stop layer 40 in the fuse opening 92 in a second etch stage.

摘要翻译： 使用专门的2级蚀刻工艺在保险丝开口（或窗口）92中的熔丝16上方形成蚀刻停止层40的方法。 本发明具有两个重要特征：首先，蚀刻停止层40由用于在基板上制造半导体器件的多晶硅层（P2或P4）形成。 蚀刻停止层40优选由多晶硅层形成，用于从接触到衬底10（P2）或形成电容器（P4）的一部分。 第二，使用专门的两级蚀刻工艺，其中第二阶段蚀刻蚀刻停止层40，同时在金属焊盘85上形成钝化层114.该方法包括：在保险丝区域15上方的所述隔离区域10上形成保险丝16 ; 形成覆盖保险丝16的第一电介质层30; 在第一介电层30上形成蚀刻停止层40; 在所述蚀刻停止层上形成绝缘层43; 在绝缘层43中通过在第一蚀刻阶段中蚀刻完整的熔融光致抗蚀剂开口90A并停止蚀刻停止层40上的第一蚀刻阶段来在绝缘层43中形成熔丝开口92; 并且在第二蚀刻阶段通过熔丝开口92中的蚀刻停止层40进行蚀刻。

公开(公告)号：US5942446A

公开(公告)日：1999-08-24

申请号：US928235

申请日：1997-09-12

申请人： Chao-Cheng Chen ,  Chen-Hua Yu

发明人： Chao-Cheng Chen ,  Chen-Hua Yu

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/00

CPC分类号： H01L21/31144 ,  H01L21/31116 ,  H01L21/76802

摘要： A method for forming a patterned silicon containing dielectric layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a silicon containing dielectric layer. There is then formed upon the silicon containing dielectric layer a hard mask layer, where the hard mask layer leaves exposed a portion of the silicon containing dielectric layer. There is then etched partially through a first plasma etch method the silicon containing dielectric layer to form a partially etched silicon containing dielectric layer. The first plasma etch method employs a first etchant gas composition comprising a first fluorocarbon etchant gas which predominantly forms a fluoropolymer layer upon at least the hard mask layer. Finally, there is then etched through a second plasma etch method the partially etched silicon containing dielectric layer to form a patterned silicon containing dielectric layer. The second plasma etch method employs a second etchant gas composition comprising a second fluoro etchant gas which predominantly etches the partially etched silicon containing dielectric layer in forming the patterned silicon containing dielectric layer.

摘要翻译： 一种用于在微电子制造中形成图案化含硅介电层的方法。 首先提供了在微电子制造中使用的衬底。 然后在衬底上形成含硅介电层。 然后在含硅电介质层上形成硬掩模层，其中硬掩模层离开暴露一部分含硅电介质层。 然后通过第一等离子体蚀刻方法将含硅介电层部分地蚀刻以形成部分蚀刻的含硅介电层。 第一等离子体蚀刻方法采用第一蚀刻剂气体组合物，其包括在至少硬掩模层上主要形成含氟聚合物层的第一碳氟化合物蚀刻剂气体。 最后，然后通过第二等离子体蚀刻方法蚀刻部分蚀刻的含硅介电层，以形成图案化的含硅介电层。 第二等离子体蚀刻方法采用包含第二氟蚀刻剂气体的第二蚀刻剂气体组合物，其主要在形成图案化的含硅介电层时蚀刻部分蚀刻的含硅介电层。

公开(公告)号：US5807789A

公开(公告)日：1998-09-15

申请号：US821353

申请日：1997-03-20

申请人： Chao-Cheng Chen ,  C. S. Tsai ,  C. H. Yu

发明人： Chao-Cheng Chen ,  C. S. Tsai ,  C. H. Yu

IPC分类号： H01L21/3065 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/3065 ,  H01L21/76232 ,  Y10S438/978

摘要： The present invention is a method for forming a shallow trench with tapered profile and round corners for the application of shallow trench isolation (STI). This invention utilizes a multiple-step dry etching process with reduced RF power and increased pressure to etch a shallow trench. This takes advantage of different degree of polymer deposition in different steps by varing the pressure and the RF power. Thus, a shallow trench with tapered profile and round corners is achieved.

摘要翻译： 本发明是用于形成具有锥形轮廓和圆角的浅沟槽的方法，用于应用浅沟槽隔离（STI）。 本发明利用具有降低的RF功率和增加的压力来蚀刻浅沟槽的多级干蚀刻工艺。 这通过改变压力和RF功率在不同步骤中利用不同程度的聚合物沉积。 因此，实现了具有锥形轮廓和圆角的浅沟槽。

公开(公告)号：US08772183B2

公开(公告)日：2014-07-08

申请号：US13277552

申请日：2011-10-20

申请人： Tzu-Yen Hsieh ,  Chang Ming-Ching ,  Chun-Hung Lee ,  Yih-Ann Lin ,  De-Fang Chen ,  Chao-Cheng Chen

发明人： Tzu-Yen Hsieh ,  Chang Ming-Ching ,  Chun-Hung Lee ,  Yih-Ann Lin ,  De-Fang Chen ,  Chao-Cheng Chen

IPC分类号： H01L21/00

CPC分类号： H01L21/0338 ,  H01L21/0276 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/32139 ,  H01L21/32155

摘要： A method of forming an integrated circuit is disclosed. A second material layer is formed on a first material layer. A patterned mask layer having a plurality of first features with a first pitch P1 is formed on the second material layer. The second material layer is etched by using the patterned mask layer as a mask to form the first features in the second material layer. The patterned mask layer is trimmed. A plurality of dopants is introduced into the second material layer not covered by the trimmed patterned mask layer. The trimmed patterned mask layer is removed to expose un-doped second material layer. The un-doped second material layer is selectively removed to form a plurality of second features with a second pitch P2. P2 is smaller than P1.

摘要翻译： 公开了形成集成电路的方法。 在第一材料层上形成第二材料层。 具有第一间距P1的多个第一特征的图案化掩模层形成在第二材料层上。 通过使用图案化掩模层作为掩模来蚀刻第二材料层，以形成第二材料层中的第一特征。 图案化掩模层被修整。 将多个掺杂剂引入到未被修整的图案化掩模层覆盖的第二材料层中。 去除修整的图案化掩模层以暴露未掺杂的第二材料层。 选择性地去除未掺杂的第二材料层以形成具有第二间距P2的多个第二特征。 P2小于P1。