公开(公告)号：US20110215300A1

公开(公告)日：2011-09-08

申请号：US12719058

申请日：2010-03-08

申请人： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

发明人： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

IPC分类号： H01L27/088 ,  H01L21/8256

CPC分类号： H01L27/0688 ,  H01L29/1606 ,  Y10S977/755

摘要： A three-dimensional (3D) integrated circuit (IC) structure includes a first layer of graphene formed over a substrate; a first level of one or more active devices formed using the first layer of graphene; an insulating layer formed over the first level of one or more active devices; a second layer of graphene formed over the insulating layer; and a second level of one or more active devices formed using the second layer of graphene, the second level of one or more active devices electrically interconnected with the first level of one or more active devices.

摘要翻译： 三维（3D）集成电路（IC）结构包括在衬底上形成的第一层石墨烯; 使用第一层石墨烯形成的一个或多个有源器件的第一级; 绝缘层，形成在一个或多个有源器件的第一级上; 在所述绝缘层上形成的第二层石墨烯; 以及使用第二层石墨烯形成的一个或多个有源器件的第二电平，一个或多个有源器件的第二电平与一个或多个有源器件的第一电平电互连。

公开(公告)号：US09142660B2

公开(公告)日：2015-09-22

申请号：US13611113

申请日：2012-09-12

申请人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

发明人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66

CPC分类号： H01L29/78 ,  H01L21/823487 ,  H01L21/823885 ,  H01L29/4983 ,  H01L29/66666 ,  H01L29/7827

摘要： A transistor structure is formed to include a substrate and, overlying the substrate, a source; a drain; and a channel disposed vertically between the source and the drain. The channel is coupled to a gate conductor that surrounds the channel via a layer of gate dielectric material that surrounds the channel. The gate conductor is composed of a first electrically conductive material having a first work function that surrounds a first portion of a length of the channel and a second electrically conductive material having a second work function that surrounds a second portion of the length of the channel. A method to fabricate the transistor structure is also disclosed. The transistor structure can be characterized as being a vertical field effect transistor having an asymmetric gate.

摘要翻译： 晶体管结构被形成为包括衬底和覆盖衬底的源极; 排水 以及垂直设置在源极和漏极之间的通道。 通道耦合到栅极导体，该栅极导体通过围绕该沟道的栅极电介质材料层围绕该沟道。 栅极导体由具有围绕通道长度的第一部分的第一功函数的第一导电材料和具有围绕通道长度的第二部分的第二功函数的第二导电材料组成。 还公开了制造晶体管结构的方法。 晶体管结构可以表征为具有非对称栅极的垂直场效应晶体管。

公开(公告)号：US09041057B2

公开(公告)日：2015-05-26

申请号：US13551164

申请日：2012-07-17

申请人： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin

发明人： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/78 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4236 ,  H01L29/66621

摘要： A field effect transistor device includes a substrate, a silicon germanium (SiGe) layer disposed on the substrate, gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity, a source region, and a drain region.

摘要翻译： 场效应晶体管器件包括衬底，设置在衬底上的硅锗（SiGe）层，衬在由衬底和硅锗层限定的空腔的表面上的栅介质层，栅极介电层上的金属栅极材料， 填充空腔的金属栅极材料，源极区域和漏极区域。

公开(公告)号：US08916405B2

公开(公告)日：2014-12-23

申请号：US13270362

申请日：2011-10-11

申请人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

发明人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

IPC分类号： H01L21/00 ,  H01L33/26 ,  H01L33/00

CPC分类号： H01L33/0041 ,  H01L33/26 ,  H01L33/34 ,  H01L33/40 ,  H01L51/0048 ,  H01L51/5203 ,  H01L51/5296

摘要： Carbon-based light emitting diodes (LEDs) and techniques for the fabrication thereof are provided. In one aspect, a LED is provided. The LED includes a substrate; an insulator layer on the substrate; a first bottom gate and a second bottom gate embedded in the insulator layer; a gate dielectric on the first bottom gate and the second bottom gate; a carbon material on the gate dielectric over the first bottom gate and the second bottom gate, wherein the carbon material serves as a channel region of the LED; and metal source and drain contacts to the carbon material.

摘要翻译： 提供了碳基发光二极管（LED）及其制造技术。 一方面，提供一种LED。 LED包括基板; 衬底上的绝缘体层; 嵌入在绝缘体层中的第一底栅极和第二底栅极; 第一底栅极和第二底栅极上的栅极电介质; 在第一底栅极和第二底栅上的栅极电介质上的碳材料，其中碳材料用作LED的沟道区域; 并且金属源极和漏极接触到碳材料。

公开(公告)号：US08866214B2

公开(公告)日：2014-10-21

申请号：US13271812

申请日：2011-10-12

申请人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

发明人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/49

CPC分类号： H01L29/78 ,  H01L21/823487 ,  H01L21/823885 ,  H01L29/4983 ,  H01L29/66666 ,  H01L29/7827

摘要： A transistor structure is formed to include a substrate and, overlying the substrate, a source; a drain; and a channel disposed vertically between the source and the drain. The channel is coupled to a gate conductor that surrounds the channel via a layer of gate dielectric material that surrounds the channel. The gate conductor is composed of a first electrically conductive material having a first work function that surrounds a first portion of a length of the channel and a second electrically conductive material having a second work function that surrounds a second portion of the length of the channel. A method to fabricate the transistor structure is also disclosed. The transistor structure can be characterized as being a vertical field effect transistor having an asymmetric gate.

摘要翻译： 晶体管结构被形成为包括衬底和覆盖衬底的源极; 排水 以及垂直设置在源极和漏极之间的通道。 通道耦合到栅极导体，该栅极导体通过围绕该沟道的栅极电介质材料层围绕该沟道。 栅极导体由具有围绕通道长度的第一部分的第一功函数的第一导电材料和具有围绕通道长度的第二部分的第二功函数的第二导电材料组成。 还公开了制造晶体管结构的方法。 晶体管结构可以表征为具有非对称栅极的垂直场效应晶体管。

公开(公告)号：US20140076738A1

公开(公告)日：2014-03-20

申请号：US13618564

申请日：2012-09-14

申请人： Shu-Jen Han ,  Lian Guo ,  Xuesong Li

发明人： Shu-Jen Han ,  Lian Guo ,  Xuesong Li

IPC分类号： C25F3/02

CPC分类号： C25F7/00 ,  B32B38/10 ,  C01B32/186 ,  C25F3/02 ,  C25F5/00

摘要： An electroplating etching apparatus includes a power supply to output current, and a container configured to contain an electrolyte. A cathode is coupled to the container and configured to fluidly communicate with the electrolyte. An anode is electrically connected to the output, and includes a graphene layer. A metal substrate layer is formed on the graphene layer, and is etched from the graphene layer in response to the current flowing through the anode.

摘要翻译： 电镀蚀刻装置包括用于输出电流的电源和构造成容纳电解质的容器。 阴极耦合到容器并且构造成与电解液流体连通。 阳极电连接到输出端，并且包括石墨烯层。 在石墨烯层上形成金属基底层，并响应于流过阳极的电流从石墨烯层中蚀刻出金属基底层。

公开(公告)号：US20140070284A1

公开(公告)日：2014-03-13

申请号：US13610158

申请日：2012-09-11

申请人： Damon B. Farmer ,  Aaron D. Franklin ,  Shu-Jen Han ,  George S. Tulevski

发明人： Damon B. Farmer ,  Aaron D. Franklin ,  Shu-Jen Han ,  George S. Tulevski

IPC分类号： H01L29/78 ,  H01L21/336 ,  B82Y99/00 ,  B82Y40/00

CPC分类号： H01L29/78669 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/78678 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0516 ,  Y10S977/742

摘要： Self-aligned carbon nanostructure field effect transistor structures are provided, which are formed using selective dielectric deposition techniques. For example, a transistor device includes an insulating substrate and a gate electrode embedded in the insulating substrate. A dielectric deposition-prohibiting layer is formed on a surface of the insulating substrate surrounding the gate electrode. A gate dielectric is selectively formed on the gate electrode. A channel structure (such as a carbon nanostructure) is disposed on the gate dielectric A passivation layer is selectively formed on the gate dielectric. Source and drain contacts are formed on opposing sides of the passivation layer in contact with the channel structure. The dielectric deposition-prohibiting layer prevents deposition of dielectric material on a surface of the insulating layer surrounding the gate electrode when selectively forming the gate dielectric and passivation layer.

摘要翻译： 提供了使用选择性电介质沉积技术形成的自对准碳纳米结构场效应晶体管结构。 例如，晶体管器件包括绝缘衬底和嵌入绝缘衬底中的栅电极。 在围绕栅电极的绝缘基板的表面上形成介电沉积禁止层。 选择性地在栅电极上形成栅极电介质。 沟道结构（例如碳纳米结构）设置在栅极电介质上钝化层选择性地形成在栅极电介质上。 源极和漏极触点形成在与沟道结构接触的钝化层的相对侧上。 当选择性地形成栅极电介质和钝化层时，介电沉积禁止层防止介电材料沉积在围绕栅电极的绝缘层的表面上。

公开(公告)号：US08623717B2

公开(公告)日：2014-01-07

申请号：US13494635

申请日：2012-06-12

申请人： Ching-Tzu Chen ,  Shu-Jen Han

发明人： Ching-Tzu Chen ,  Shu-Jen Han

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L29/78 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/1606 ,  H01L29/42384 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/78645 ,  H01L29/78648

摘要： A method to fabricate a novel graphene based, electrically tunable, nanoconstriction device is described. The device includes a back-gate dielectric layer formed over a conductive substrate. The back-gate dielectric layer is, in one example, hexagonal boron nitride, mica, SiOx, SiNx, BNx, HfOx or AlOx. A graphene layer is an AB-stacked bi-layer graphene layer, an ABC-stacked tri-layer graphene layer or a stacked few-layer graphene layer. Contacts are formed over a portion of the graphene layer including at least one source contact, at least one drain contact and at least one set of side-gate contacts. A graphene channel with graphene side gates is formed in the graphene layer between the at least one source contact, the at least one the drain contact and the at least one set of side-gate contacts. A top-gate dielectric layer is formed over the graphene layer. A top-gate electrode is formed on the top-gate dielectric layer.

摘要翻译： 描述了制造新的基于石墨烯的电可调谐纳米收缩装置的方法。 该器件包括形成在导电衬底上的背栅电介质层。 在一个示例中，背栅电介质层是六方氮化硼，云母，SiOx，SiNx，BNx，HfOx或AlOx。 石墨烯层是AB层叠的双层石墨烯层，ABC层叠的三层石墨烯层或层叠的几层石墨烯层。 触点形成在石墨烯层的一部分上，包括至少一个源极接触，至少一个漏极接触和至少一组侧栅接触。 具有石墨烯侧栅极的石墨烯通道在所述至少一个源极接触件，所述至少一个漏极接触件和所述至少一组侧栅极接触件之间的石墨烯层中形成。 在石墨烯层上形成顶栅电介质层。 顶栅电极形成在顶栅电介质层上。

公开(公告)号：US08569135B2

公开(公告)日：2013-10-29

申请号：US13186597

申请日：2011-07-20

申请人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

发明人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

IPC分类号： H01L21/8234

CPC分类号： H01L29/42364 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

摘要： In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function material portion to form a gate structure that enhances performance of a replacement gate field effect transistor.

摘要翻译： 在替代栅极方案中，连续材料层沉积在栅极腔中的底表面和侧壁表面上。 去除连续材料层的垂直部分以形成垂直部分不延伸到栅极腔的顶部的栅极部件。 栅极元件可以用作栅极电介质或功函数材料部分，以形成增强替代栅极场效应晶体管性能的栅极结构。

公开(公告)号：US20130153964A1

公开(公告)日：2013-06-20

申请号：US13326825

申请日：2011-12-15

申请人： Dechao Guo ,  Shu-Jen Han ,  Edward William Kiewra ,  Kuen-Ting Shiu

发明人： Dechao Guo ,  Shu-Jen Han ,  Edward William Kiewra ,  Kuen-Ting Shiu

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/8258 ,  H01L21/823807 ,  H01L27/0605

摘要： Techniques for employing different channel materials within the same CMOS circuit are provided. In one aspect, a method of fabricating a CMOS circuit includes the following steps. A wafer is provided having a first semiconductor layer on an insulator. STI is used to divide the first semiconductor layer into a first active region and a second active region. The first semiconductor layer is recessed in the first active region. A second semiconductor layer is epitaxially grown on the first semiconductor layer, wherein the second semiconductor layer comprises a material having at least one group III element and at least one group V element. An n-FET is formed in the first active region using the second semiconductor layer as a channel material for the n-FET. A p-FET is formed in the second active region using the first semiconductor layer as a channel material for the p-FET.

摘要翻译： 提供在同一CMOS电路内采用不同通道材料的技术。 一方面，制造CMOS电路的方法包括以下步骤。 提供了在绝缘体上具有第一半导体层的晶片。 STI用于将第一半导体层分成第一有源区和第二有源区。 第一半导体层凹入第一有源区。 第二半导体层在第一半导体层上外延生长，其中第二半导体层包括具有至少一个III族元素和至少一个V族元素的材料。 使用第二半导体层作为n-FET的沟道材料，在第一有源区中形成n-FET。 使用第一半导体层作为p-FET的沟道材料，在第二有源区中形成p-FET。