公开(公告)号：US09628106B1

公开(公告)日：2017-04-18

申请号：US15007054

申请日：2016-01-26

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Ali Hadiashar ,  Eric King ,  David Entrikin ,  Wai Lang Lee

IPC: H03M3/00

CPC classification number: H03M3/496 ,  H03M3/376 ,  H03M3/438

Abstract: Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.

公开(公告)号：US09544690B2

公开(公告)日：2017-01-10

申请号：US14550545

申请日：2014-11-21

Applicant: Avnera Corporation

Inventor： Theodore Hetke ,  John Speth

IPC: H04R3/12 ,  H04W4/00

CPC classification number: H04R3/12 ,  H04R2420/07 ,  H04R2420/09 ,  H04R2430/01 ,  H04W4/80

Abstract: A method for forming a complete ring network of a plurality of Bluetooth® speakers, the method including populating a configurable speaker register of each of the plurality of Bluetooth® speakers with an address of an upstream Bluetooth® speaker that is in the plurality of Bluetooth® speakers, populating the configurable speaker register of each of the plurality of Bluetooth® speakers with an address of a downstream Bluetooth® speaker that is in the plurality of Bluetooth® speakers, and coupling an audio source to one Bluetooth® speaker of the plurality of Bluetooth® speakers.

Abstract translation: 一种用于形成多个蓝牙扬声器的完整环形网络的方法，所述方法包括用多个蓝牙®扬声器中的上游蓝牙扬声器的地址填充多个蓝牙扬声器中的每一个的可配置扬声器寄存器 扬声器，用多个Bluetooth®扬声器中的下游蓝牙扬声器的地址填充多个蓝牙扬声器中的每一个的可配置扬声器寄存器，并将音频源耦合到多个蓝牙的蓝牙扬声器 ®扬声器

公开(公告)号：US09531400B1

公开(公告)日：2016-12-27

申请号：US14932798

申请日：2015-11-04

Applicant: AVNERA CORPORATION

Inventor： Jianping Wen ,  Garry Link ,  Wai Lee

IPC: H03M1/06 ,  H03M1/40 ,  H03M1/44 ,  H03M1/46

CPC classification number: H03M1/1009 ,  H03M1/0682 ,  H03M1/0692 ,  H03M1/38 ,  H03M1/403 ,  H03M1/462 ,  H03M1/468 ,  H03M1/804

Abstract: A circuit can include a voltage comparator Vd having a first input, a second input, and an output; a first plurality of capacitors Cp[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with a common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a first input voltage Vinp, a reference voltage Vref, the common mode voltage Vcm, and ground; a second plurality of capacitors Cn[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the second input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with the common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a second input voltage Vinn, the reference voltage Vref, the common mode voltage Vcm, and ground; and a successive approximation register (SAR) controller coupled with the output of the voltage comparator Vd.

Abstract translation: 电路可以包括具有第一输入，第二输入和输出的电压比较器Vd; 具有顶板和底板的第一多个电容器Cp [0：n]，其中每个顶板与电压比较器Vd的第一输入电耦合，其中每个顶板也可切换地电耦合到 共模电压Vcm，并且其中每个底板可切换地电耦合在第一输入电压Vinp，参考电压Vref，共模电压Vcm和地之间; 分别具有顶板和底板的第二多个电容器Cn [0：n]，其中每个顶板与电压比较器Vd的第二输入电耦合，其中每个顶板也可切换地电耦合到 共模电压Vcm，并且其中每个底板可切换地电耦合在第二输入电压Vinn，参考电压Vref，共模电压Vcm和地之间; 以及与电压比较器Vd的输出耦合的逐次逼近寄存器（SAR）控制器。

公开(公告)号：US20150195646A1

公开(公告)日：2015-07-09

申请号：US14148533

申请日：2014-01-06

Applicant: Avnera Corporation

Inventor： Amit Kumar ,  Wai Lang Lee ,  Jianping Wen

IPC: H04R3/00

CPC classification number: G10K11/178 ,  G10K11/17853 ,  G10K11/17873 ,  G10K11/17875 ,  G10K11/17879 ,  G10K2210/3016 ,  G10K2210/3026 ,  G10K2210/3027 ,  G10K2210/3028 ,  H04R2460/01

Abstract: A programmable Active Noise Compensation (ANC) system for an audio input includes a parameter store structured to store a number of various filter parameters. A mode of operation is selected that represents the type of environment the ANC system is operating in—feed-forward, feed-back, or combined feed-forward and feedback. Different filter parameters are retrieved from the parameter store based on the selected mode and desired operation. Audio inputs are sampled at a relatively high sample rate that matches inputs from a feed-forward and feedback microphone that may be present in the system. Parameters and instructions may be changed in the system responsive to changing conditions of the compensation system.

Abstract translation: 用于音频输入的可编程有源噪声补偿（ANC）系统包括结构化以存储多个滤波器参数的参数存储器。 选择一种操作模式，其表示ANC系统正在进行前馈，反馈或组合的前馈和反馈的环境类型。 基于所选择的模式和期望的操作，从参数存储器检索不同的滤波器参数。 音频输入以相对高的采样率进行采样，该采样率与可能存在于系统中的前馈和反馈麦克风的输入相匹配。 响应于补偿系统的变化条件，可以在系统中改变参数和指令。

公开(公告)号：US20150193193A1

公开(公告)日：2015-07-09

申请号：US14249696

申请日：2014-04-10

Applicant: Avnera Corporation

Inventor： Manpreet S. Khaira ,  Shawn O'Connor ,  Frank Prestrelski ,  Patrick Allen Quinn ,  Richard Andrew Sorensen ,  Eric Sorensen

IPC: G06F3/16

CPC classification number: G06F3/162 ,  G06F3/017 ,  G06F3/0304 ,  G06F3/0346 ,  G06F3/0414 ,  G06F3/165 ,  G06F3/167 ,  G06F2200/1636 ,  H04R2201/02 ,  H04R2430/01

Abstract: A tabletop speaker system includes an amplifier, proximity and acceleration detectors, and a processor. The processor is operatively coupled to receive signals from the proximity and accelerometer detectors, and in response to the proximity and acceleration signals, activate various functions local to the tabletop speaker system to operate and control various behaviors or features of the tabletop speaker system. In this way, the tabletop speaker system can respond to user gestures for a very natural control interface.

Abstract translation: 台式扬声器系统包括放大器，接近和加速度检测器以及处理器。 处理器可操作地耦合以从接近和加速度计检测器接收信号，并且响应于接近和加速度信号，激活桌面扬声器系统的局部的各种功能来操作和控制台式扬声器系统的各种行为或特征。 以这种方式，桌面扬声器系统可以响应用户手势进行非常自然的控制界面。

公开(公告)号：US08848849B1

公开(公告)日：2014-09-30

申请号：US13800557

申请日：2013-03-13

Applicant: Avnera Corporation

Inventor： Samuel J. Peters ,  Eric P. Etheridge ,  Victor Lee Hanson ,  Alexander C. Stange

IPC: H04L7/02

CPC classification number: H04L7/027 ,  G06F13/4295 ,  H04L7/0029 ,  H04L7/02

Abstract: A system and a technique for recovering data from an input data stream without synchronization of an input sampling circuit to the input data stream determines a count of incoming samples (or frames) without generating a signal that is frequency-locked to the input data stream. A first clock is generated comprising a frequency that is greater than or equal to an expected frequency of the input data stream. A sample count is incremented in response to a sample received in the input data stream, and is decremented in response to a second clock signal. The second clock is generated the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value.

Abstract translation: 用于从输入数据流中恢复数据而不输入输入采样电路与输入数据流的同步的系统和技术确定输入采样（或帧）的计数，而不产生频率锁定到输入数据流的信号。 产生包括大于或等于输入数据流的预期频率的频率的第一时钟。 响应于在输入数据流中接收到的采样，采样计数递增，并且响应于第二时钟信号递减。 如果采样计数器的采样计数不等于预定采样计数值，并且如果采样计数等于预定采样计数值则阻塞第一时钟信号，则通过传递第一时钟信号来产生第二时钟信号。

公开(公告)号：US20140195716A1

公开(公告)日：2014-07-10

申请号：US13738709

申请日：2013-01-10

Applicant: Avnera Corporation

Inventor： Ole Bentz ,  Robert Mays ,  Bruce Nepple ,  James Anderson

IPC: G06F12/02

CPC classification number: G06F12/0223 ,  G06F12/0638 ,  G06F2212/1012 ,  G06F2212/205

Abstract: A memory address space for each of a plurality of physical memories in a microprocessor-based system is allocated prior to knowing the desired logical size of at least one of the physical memories. At least two of the allocated memory address spaces overlap at least a portion of each other. After the system is fabricated, a pointer value set that corresponds to an address boundary between at least two physical memories of the fabricated system is set during boot time and/or during run time when the size of the physical memories are known. The technique provides a faster time-to-market for microprocessor-based systems by allowing, for example, Application Specific Integrated Circuits (ASICs) comprising microprocessor systems on-chip be manufactured prior to the final firmware and software being fully developed. Additionally, the subject matter disclosed herein permits changes in memory-space allocation for finalized ASIC designs.

Abstract translation: 在知道至少一个物理存储器的期望的逻辑大小之前，分配用于基于微处理器的系统中的多个物理存储器中的每一个的存储器地址空间。 所分配的存储器地址空间中的至少两个与彼此的至少一部分重叠。 在制造系统之后，在引导时间期间和/或在运行时间期间设置物理存储器的大小已知时，设置对应于所制造的系统的至少两个物理存储器之间的地址边界的指针值集合。 该技术通过允许例如在最终固件和软件完全开发之前制造包括芯片上的微处理器系统的专用集成电路（ASIC）来为基于微处理器的系统提供更快的上市时间。 此外，本文公开的主题允许最终ASIC设计的存储空间分配的改变。

公开(公告)号：US08228111B2

公开(公告)日：2012-07-24

申请号：US12154285

申请日：2008-05-20

Applicant: Patrick A. Quinn

Inventor： Patrick A. Quinn

IPC: H03K17/56

CPC classification number: H03F3/2173 ,  H03F1/0211 ,  H03F1/523

Abstract: A circuit architecture, or topology, that provides a level shifter substantially independent of the duty cycle of an input signal includes an H-bridge arrangement of field effect transistors, a pair of capacitively coupled input terminals connected to the gates of the high-side transistors and circuitry to set the bias voltage at the gates of the high-side transistors, wherein the bias voltage generation circuitry receives at least information indicative of both the H-bridge power supply voltage and the modulation of the input signal. Various embodiments include a switchable element coupled in series with a voltage divider portion in the bias voltage generation circuitry. The ratio of on to off time of the switchable element determines the average current through the voltage divider and thus the bias voltage. To prevent excessive short-circuit current flow through the high-side transistors, the switchable elements are turned off responsive to detection of a short-circuit condition.

Abstract translation: 提供基本上独立于输入信号的占空比的电平移位器的电路架构或拓扑结构包括场效应晶体管的H桥布置，连接到高侧晶体管的栅极的一对电容耦合输入端 以及用于在高侧晶体管的栅极处设置偏置电压的电路，其中偏置电压产生电路至少接收表示H桥电源电压和输入信号的调制的信息。 各种实施例包括与偏置电压产生电路中的分压器部分串联耦合的可切换元件。 可切换元件的导通到关断时间的比率决定了通过分压器的平均电流，从而确定了偏置电压。 为了防止通过高侧晶体管的过大的短路电流流过，可切换元件响应于短路状况的检测而被关断。

公开(公告)号：US07467344B2

公开(公告)日：2008-12-16

申请号：US11317705

申请日：2005-12-23

Applicant: Debarag Narayan Banerjee

Inventor： Debarag Narayan Banerjee

IPC: H03M13/00

CPC classification number: H03M13/2909 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/6306 ,  H04L1/0041 ,  H04L1/0057 ,  H04L1/0065 ,  H04L1/0071

Abstract: Systems and methods for communicating source data between a source device and a listener device are disclosed. In an exemplary embodiment, source data is encoded by organizing at least a selected portion of source data into a data block having rows and columns. Encoded columns are formed by appending to each column error correction data derived from that column using a selected error correction code. Encoded rows are formed by appending to each row error correction data derived from that row using a selected error correct code. In an exemplary embodiment, encoded rows of source data (together with appended FEC data) and a first predetermined number of rows of FEC data are transmitted together, such that the first predetermined number of rows is less than all rows of error correction data. In an exemplary embodiment, source data is organized using interleaving.

Abstract translation: 公开了在源设备和收听设备之间传送源数据的系统和方法。 在示例性实施例中，通过将至少一个源数据的所选部分组织成具有行和列的数据块来对源数据进行编码。 编码列通过使用选择的纠错码附加到从列导出的每列错误校正数据而形成。 编码行通过使用所选择的错误正确代码附加到从该行导出的每行错误校正数据而形成。 在示例性实施例中，一起发送源数据（连同附加的FEC数据）和第一预定数量的FEC数据的编码行，使得第一预定数量的行小于所有行的纠错数据。 在示例性实施例中，使用交织来组织源数据。

公开(公告)号：US11133785B2

公开(公告)日：2021-09-28

申请号：US16648621

申请日：2018-09-20

Applicant: Avnera Corporation

Inventor： Wai Laing Lee

IPC: H03F3/217 ,  H03F3/187 ,  H03M1/46 ,  H03M1/50 ,  H03M1/82 ,  H04R3/00 ,  H03F3/45 ,  H03M3/00

Abstract: An amplifier for headphones including a current digital-to-analog converter (DAC) configured to output a current based on a digital audio input signal, an output electrically connected to a speaker and configured to output an output signal to the speaker, and a pulse width modulation (PWM) loop configured to receive an error signal, the error signal based on a difference between the current from the current DAC and a current of the output signal, and generate the output signal based on the error signal. The PWM loop includes an analog-to-digital converter (ADC) configured to receive an analog signal based on the current from the current DAC and output a digital signal representing the analog signal, and an encoder configured to receive the digital signal and output a pulse having a width based on the analog signal.