公开(公告)号：US20180277532A1

公开(公告)日：2018-09-27

申请号：US15764394

申请日：2016-08-24

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Zheng BIAN

IPC: H01L27/02

CPC classification number: H01L27/0255 ,  H01L27/0629 ,  H01L29/0657 ,  H01L29/16 ,  H01L29/7801 ,  H01L29/866

Abstract: A semiconductor device, having an electro-static discharge (ESD) protection structure, comprises: a diode, connected between a gate and a source of the semiconductor device, and comprising a diode main body, and two connection portions, respectively connected to two terminals of the diode main body and respectively electrically connected to the gate and the source; and a substrate comprising two insulation pads disposed thereon and separated from each other. A surface of the substrate between the insulation pads is provided with an insulation layer. The diode main body is arranged on the insulation layer. The two connection portions are configured to extend, respectively, from either end of the diode main body to the insulation pad on the corresponding side. A dielectric layer is arranged on the diode and the two insulation pads, and a metal conduction line layer is arranged on the dielectric layer.

公开(公告)号：US20180134548A1

公开(公告)日：2018-05-17

申请号：US15573280

申请日：2016-05-10

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Errong JING

IPC: B81C1/00 ,  G01J5/20

CPC classification number: B81C1/00182 ,  B81B7/02 ,  B81C1/00 ,  B81C1/00476 ,  B81C2201/0108 ,  B81C2201/0109 ,  B81C2201/0132 ,  G01J5/20

Abstract: An MEMS double-layer suspension microstructure manufacturing method, comprising: providing a substrate (100); forming a first dielectric layer (200) on the substrate (100); patterning the first dielectric layer (200) to prepare a first film body (210) and a cantilever beam (220) connected to the first film body (210); forming a sacrificial layer (300) on the first dielectric layer (200); patterning the sacrificial layer (300) located on the first film body (210) to make a recess portioned portion (310) for forming a support structure (420), with the first film body (210) being exposed at the bottom of the recess portioned portion (310); forming a second dielectric layer (400) on the sacrificial layer (300); patterning the second dielectric layer (400) to make the second film body (410) and the support structure (420), with the support structure (420) being connected to the first film body (210) and the second film body (410); and removing part of the substrate under the first film body (210) and removing the sacrificial layer (300) to obtain the MEMS double-layer suspension microstructure. In addition, an MEMS infrared detector is also disclosed.

公开(公告)号：US20180122794A1

公开(公告)日：2018-05-03

申请号：US15569848

申请日：2016-04-29

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Jun SUN ,  Zhongyu LIN ,  Guangyang WANG ,  Guipeng SUN

IPC: H01L27/02 ,  H01L29/78

CPC classification number: H01L27/0262 ,  H01L29/402 ,  H01L29/7817 ,  H01L29/87

Abstract: An electrostatic protection device of an LDMOS silicon controlled structure comprises a P-type substrate (310), an N-well (320) and a P-well (330) on the substrate, a gate electrode (340) overlapping on the P-well (330) and extending to an edge of the N-well (320), a first N+ structure and a first P+ structure provided in the N-well (320), and a second N+ structure and a second P+ structure provided in the P-well(330), the first N+ structure being a drain electrode N+ structure (322), the first N+ structure being a drain electrode N+ structure (322), the first P+ structure being a drain electrode P+ structure (324), the second N+ structure being a source electrode N+ structure (332), the second P+ structure being a source P+ structure (334), and a distance from the drain electrode P+ structure (324) to the gate electrode (340) being greater than a distance from the drain electrode N+ structure (322) to the gate electrode (340).

公开(公告)号：US20180006043A1

公开(公告)日：2018-01-04

申请号：US15547278

申请日：2015-09-23

Applicant: CSMC TECHNOLOGIES CO., LTD

Inventor： Guipeng SUN ,  Qiong WANG ,  Guangtao HAN

IPC: H01L27/112 ,  H01L21/265 ,  H01L21/266 ,  H01L29/06

CPC classification number: H01L27/11266 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/0607 ,  H01L29/66492

Abstract: A preparation method for a flat cell ROM device, comprising the steps of: providing a substrate, and forming a P well on the substrate; forming a photomask layer on the P well and performing photoetching to form an injection window; injecting P-type ions in the formed injection window to form a P-type region; injecting N-type ions in the injection window so as to form an N-type region on the P-type region; and forming a gate oxide layer and a poly-silicon gate so as to complete the preparation of a device.

公开(公告)号：US09368505B2

公开(公告)日：2016-06-14

申请号：US14130470

申请日：2012-08-02

Applicant: Kai Huang ,  Peng Du ,  Jianxiang Cai ,  Tsung-nten Hsu

Inventor： Kai Huang ,  Peng Du ,  Jianxiang Cai ,  Tsung-nten Hsu

IPC: H01L27/112 ,  H01L27/02

CPC classification number: H01L27/112 ,  H01L27/0207 ,  H01L27/11266

Abstract: A read-only memory includes a plurality of storage units arranged in an array. The read-only memory includes two kinds of storage units with different structures, the two kinds of storage units with different structures are a first MOS transistor and a second MOS transistor. A source and a drain of the first MOS transistor have the same type, a source and a drain of the second MOS transistor have inverse type. These two kinds of MOS transistors can be used to store binary 0 and 1 respectively. In the manufacturing method of the read-only memory, the same type of drain and source can be manufactured simultaneously, no extra mask plate is needed, so the extra mask plate of a conventional read-only memory can be saved.

Abstract translation: 只读存储器包括以阵列排列的多个存储单元。 只读存储器包括具有不同结构的两种存储单元，具有不同结构的两种存储单元是第一MOS晶体管和第二MOS晶体管。 第一MOS晶体管的源极和漏极具有相同类型，第二MOS晶体管的源极和漏极具有相反的类型。 这两种MOS晶体管可分别用于存储二进制0和1。 在只读存储器的制造方法中，可以同时制造相同类型的漏极和源极，不需要额外的掩模板，因此可以节省常规只读存储器的额外掩模板。

公开(公告)号：US09166399B2

公开(公告)日：2015-10-20

申请号：US13807635

申请日：2011-11-29

Applicant: Shunhui Lei

Inventor： Shunhui Lei

IPC: H02J7/00 ,  H02H7/18

CPC classification number: H02H7/18 ,  H02J7/0029 ,  H02J7/0031 ,  H02J2007/0039 ,  Y02E60/12

Abstract: A lithium battery protection circuit coupled to a lithium battery is provided. The lithium battery protection circuit includes an over-charge protection circuit and a logic circuit coupled to over-charge protection circuit. The logic circuit has a first logic output and a second logic output. The lithium battery protection circuit also includes a level shift circuit coupled to the logic circuit through the first logic output and the second logic output, and the level shift circuit is configured to convert the first logic output and the second logic output to high voltage levels in an over-charge protection state. Further, the lithium battery protection circuit includes a substrate switching circuit coupled to the level shift circuit and a power transistor coupled between a negative end of the lithium battery and an external circuit negative electrode. The level shift circuit includes a first inverter coupled to the second logic output, a plurality of PMOS transistors, at least one of which has high source-drain voltage and low gate-source voltage, and a plurality of NMOS transistors, at least one of which is a low-voltage NMOS transistor.

Abstract translation: 提供耦合到锂电池的锂电池保护电路。 锂电池保护电路包括过充电保护电路和耦合到过充电保护电路的逻辑电路。 逻辑电路具有第一逻辑输出和第二逻辑输出。 锂电池保护电路还包括通过第一逻辑输出和第二逻辑输出耦合到逻辑电路的电平移位电路，并且电平移位电路被配置为将第一逻辑输出和第二逻辑输出转换成高电压电平 过充保护状态。 此外，锂电池保护电路包括耦合到电平移位电路的衬底切换电路和耦合在锂电池的负端和外部电路负极之间的功率晶体管。 电平移位电路包括耦合到第二逻辑输出的第一反相器，多个PMOS晶体管，其中至少一个具有高源极 - 漏极电压和低栅极 - 源极电压，以及多个NMOS晶体管，至少一个 其是低电压NMOS晶体管。

公开(公告)号：US08803250B2

公开(公告)日：2014-08-12

申请号：US13807308

申请日：2011-11-18

Applicant: Le Wang

Inventor： Le Wang

IPC: H01L29/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/78 ,  H01L29/1033 ,  H01L29/66477 ,  H01L29/66651

Abstract: A Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is disclosed. The MOSFET includes a substrate, a well region formed in the substrate, a shallow channel layer, a channel, a gate oxide layer, a gate region, a source region, and a drain region. The shallow channel layer is formed on a portion of the well region and includes a first shallow channel region and a second shallow channel region. The channel is arranged between the first shallow channel region and the second shallow channel region and connects the first shallow channel region and the second shallow channel region. Further, the gate oxide layer is formed on a portion of the well region between the first shallow channel region and the second shallow channel region and includes a first gate oxide region and a second gate oxide region arranged on different sides of the channel. The gate region is formed on the channel and the gate oxide layer; the source region is formed in the first shallow channel region and vertically extends into the well region under the first shallow channel region; and the drain region is formed in the second shallow channel region and vertically extends into the well region under the second shallow channel region.

Abstract translation: 公开了一种金属氧化物半导体场效应晶体管（MOSFET）。 MOSFET包括衬底，形成在衬底中的阱区，浅沟道层，沟道，栅极氧化物层，栅极区，源极区和漏极区。 浅沟道层形成在阱区的一部分上，并且包括第一浅沟道区和第二浅沟道区。 通道布置在第一浅沟道区域和第二浅沟道区域之间，并且连接第一浅沟道区域和第二浅沟道区域。 此外，栅极氧化层形成在第一浅沟道区域和第二浅沟道区域之间的阱区域的一部分上，并且包括布置在沟道的不同侧上的第​​一栅极氧化物区域和第二栅极氧化物区域。 栅极区形成在沟道和栅极氧化物层上; 源极区域形成在第一浅沟道区域中并垂直延伸到第一浅沟道区域下方的阱区域中; 并且所述漏极区域形成在所述第二浅沟道区域中并且垂直延伸到所述第二浅沟道区域下方的阱区域中。

公开(公告)号：US08772864B2

公开(公告)日：2014-07-08

申请号：US13807612

申请日：2011-11-29

Applicant: Jiakun Wang

Inventor： Jiakun Wang

IPC: H01L29/66

CPC classification number: H01L29/7827 ,  H01L29/4236 ,  H01L29/66666

Abstract: A trench Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) device is disclosed. The trench MOSFET device includes a substrate, a body region, a source region, a dielectric layer, a metal layer, a contact hole, and a trench structure. The substrate includes a substrate layer and an epitaxial layer formed on the substrate layer; the body region is formed in the epitaxial layer; and the source region is formed in the body region of the epitaxial layer. Further, the dielectric layer is formed on the epitaxial layer; the metal layer is formed on the dielectric layer; and the contact hole is formed in the dielectric layer to connect the source region with the metal layer. In addition, the trench structure is formed in the epitaxial layer, and the trench structure includes a first trench that is a pectinate trench including a plurality of tooth trenches and a bar trench interconnecting the plurality of tooth trenches.

Abstract translation: 公开了一种沟槽金属氧化物半导体场效应晶体管（MOSFET）器件。 沟槽MOSFET器件包括衬底，体区，源极区，电介质层，金属层，接触孔和沟槽结构。 衬底包括衬底层和形成在衬底层上的外延层; 在外延层中形成体区; 并且源区域形成在外延层的体区中。 此外，介电层形成在外延层上; 金属层形成在电介质层上; 并且在电介质层中形成接触孔以将源极区域与金属层连接。 此外，沟槽结构形成在外延层中，并且沟槽结构包括第一沟槽，其是包括多个齿槽的果胶沟槽和互连多个齿槽的条形沟槽。

公开(公告)号：US12249645B2

公开(公告)日：2025-03-11

申请号：US17620952

申请日：2020-05-26

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Zhili Zhang ,  Jingchuan Zhao ,  Sen Zhang

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66

Abstract: A laterally diffused metal-oxide-semiconductor (LDMOS) device and a method of manufacturing the LDMOS device are disclosed. The method includes: obtaining a substrate with a drift region formed thereon, the drift region having a first conductivity type and disposed on the substrate of a second conductivity type; etching the drift region to form therein a sinking structure, the sinking structure includes at least one of an implanting groove and an implanting hole; implanting ions of the second conductivity type at the bottom of the sinking structure; forming a buried layer of the second conductivity type by causing diffusion of the ions of the second conductivity type using a thermal treatment; and filling an electrical property modification material into the sinking structure, the electrical property modification material differs from the material of the drift region.

公开(公告)号：US20240304720A1

公开(公告)日：2024-09-12

申请号：US18576942

申请日：2022-12-14

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun JIN ,  Liang SONG ,  Yongshun LI ,  Mei YUAN ,  Yanan WANG ,  Lin LUO ,  Qiang ZHANG

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0603 ,  H01L29/66681

Abstract: The present disclosure involves a semiconductor device and a manufacturing method thereof. A second well region is inserted between first well regions of a semiconductor device to improve the breakdown voltage of the device, and at the same time, the dimension of the upper surface of the second well region in the width direction of the device's conductive channel is set to be smaller than the dimension of the lower surface of the second well region in the width direction of the device's conductive channel to increase the dimension of the upper surface of the adjacent first well region in the width direction of the device's conductive channel. That is, the path width of the current flowing through the upper surface of the drift region is increased when the device is on, and thus the device's on-resistance is reduced.