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    Method for manufacturing double-gate structures
    1.
    发明授权
    Method for manufacturing double-gate structures 有权
    双门结构的制造方法

    公开(公告)号：US08895398B2

    公开(公告)日：2014-11-25

    申请号：US13807307

    申请日：2011-11-03

    Applicant: Le Wang

    Inventor： Le Wang

    IPC: H01L21/336 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/285

    CPC classification number: H01L29/66484 ,  H01L21/28518 ,  H01L21/823443 ,  H01L21/823468

    Abstract: A method is provided for manufacturing a double-gate structure. The method includes providing a substrate and forming a first gate region on a surface of the substrate using a first gate layer. The method also includes forming a second gate layer on the surface of the substrate, wherein the second gate layer covers the first gate region, forming an etch-stop layer on the second gate layer, and forming a silicide layer on the etch-stop layer. The method also includes forming a second gate region, different from the first gate region, containing the second gate layer and the silicide layer without the etch-stop layer. Further, the etch-stop layer is arranged between the second gate layer and the silicide layer to facilitate even etching of the second gate layer around the first gate region.

    Abstract translation: 提供了一种用于制造双栅结构的方法。 该方法包括提供衬底并使用第一栅极层在衬底的表面上形成第一栅极区域。 该方法还包括在衬底的表面上形成第二栅极层，其中第二栅极层覆盖第一栅极区，在第二栅极层上形成蚀刻停止层，并在蚀刻停止层上形成硅化物层 。 该方法还包括形成不含蚀刻停止层的不含第一栅极区的第二栅极区，其包含第二栅极层和硅化物层。 此外，蚀刻停止层被布置在第二栅极层和硅化物层之间，以便于围绕第一栅极区域均匀蚀刻第二栅极层。

    Bipolar transistor and method for manufacturing the same
    2.
    发明授权
    Bipolar transistor and method for manufacturing the same 有权
    双极晶体管及其制造方法

    公开(公告)号：US08729669B2

    公开(公告)日：2014-05-20

    申请号：US13519252

    申请日：2010-12-02

    Applicant: Le Wang ,  Linchun Gui ,  Kongwei Zhu ,  Zhiyong Zhao

    Inventor： Le Wang ,  Linchun Gui ,  Kongwei Zhu ,  Zhiyong Zhao

    IPC: H01L29/02

    CPC classification number: H01L29/66272

    Abstract: A method for manufacturing a bipolar transistor includes forming a first epitaxial layer on a semiconductor substrate, forming a second epitaxial layer on the first epitaxial layer, forming an oxide layer on the second epitaxial layer, etching the oxide layer to form an opening in which the second epitaxial layer is exposed, and forming a third epitaxial layer in the opening. The first and third epitaxial layers have a first-type conductivity, and the second epitaxial layer has a second-type conductivity.

    Abstract translation: 一种用于制造双极晶体管的方法，包括在半导体衬底上形成第一外延层，在第一外延层上形成第二外延层，在第二外延层上形成氧化层，蚀刻氧化物层以形成开口， 暴露第二外延层，并在开口中形成第三外延层。 第一和第三外延层具有第一类型的导电性，第二外延层具有第二类型的导电性。

    COMPATIBLE VERTICAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR AND LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR AND MANUFACTURE METHOD THEREOF
    4.
    发明申请
    COMPATIBLE VERTICAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR AND LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR AND MANUFACTURE METHOD THEREOF 有权
    兼容的垂直双向扩散金属氧化物半导体晶体管及其双向扩散金属氧化物半导体晶体管及其制造方法

    公开(公告)号：US20120256252A1

    公开(公告)日：2012-10-11

    申请号：US13384002

    申请日：2010-10-26

    Applicant: Linchun Gui ,  Le Wang ,  Zhiyong Zhao ,  Lili He

    Inventor： Linchun Gui ,  Le Wang ,  Zhiyong Zhao ,  Lili He

    IPC: H01L29/78 ,  H01L21/8238

    CPC classification number: H01L29/66712 ,  H01L21/823418 ,  H01L21/823487 ,  H01L21/8249 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7809 ,  H01L29/7835

    Abstract: A method for manufacturing compatible vertical double diffused metal oxide semiconductor (VDMOS) transistor and lateral double diffused metal oxide semiconductor (LDMOS) transistor includes: providing a substrate having an LDMOS transistor region and a VDMOS transistor region; forming an N-buried region in the substrate; forming an epitaxial layer on the N-buried layer region; forming isolation regions in the LDMOS transistor region and the VDMOS transistor region; forming a drift region in the LDMOS transistor region; forming gates in the LDMOS transistor region and the VDMOS transistor region; forming PBODY regions in the LDMOS transistor region and the VDMOS transistor region; forming an N-type GRADE region in the LDMOS transistor region; forming an NSINK region in the VDMOS transistor region, where the NSINK region is in contact with the N-buried layer region; forming sources and drains in the LDMOS transistor region and the VDMOS transistor region; and forming a P+ region in the LDMOS transistor region, where the P+ region is in contact with the source.

    Abstract translation: 制造兼容的垂直双扩散金属氧化物半导体（VDMOS）晶体管和横向双扩散金属氧化物半导体（LDMOS）晶体管的方法包括：提供具有LDMOS晶体管区域和VDMOS晶体管区域的衬底; 在所述衬底中形成N掩埋区域; 在N掩埋层区域上形成外延层; 在LDMOS晶体管区域和VDMOS晶体管区域中形成隔离区域; 在LDMOS晶体管区域中形成漂移区; 在LDMOS晶体管区域和VDMOS晶体管区域中形成栅极; 在LDMOS晶体管区域和VDMOS晶体管区域中形成PBODY区域; 在LDMOS晶体管区域中形成N型GRADE区域; 在所述VDMOS晶体管区域中形成NSINK区域，其中所述NSINK区域与所述N埋层区域接触; 在LDMOS晶体管区域和VDMOS晶体管区域中形成源极和漏极; 以及在LDMOS晶体管区域中形成P +区域，其中P +区域与源极接触。

    METHOD FOR FABRICATING TRENCH DMOS TRANSISTOR
    7.
    发明申请
    METHOD FOR FABRICATING TRENCH DMOS TRANSISTOR 审中-公开
    用于制造TRENCH DMOS晶体管的方法

    公开(公告)号：US20120178230A1

    公开(公告)日：2012-07-12

    申请号：US13394679

    申请日：2010-09-26

    Applicant: Le Wang

    Inventor： Le Wang

    IPC: H01L21/336

    CPC classification number: H01L29/7813 ,  H01L29/42372 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66719 ,  H01L29/66734

    Abstract: A method for fabricating trench DMOS transistor includes: forming an oxide layer and a barrier layer with photolithography layout sequentially on a semiconductor substrate; etching the oxide layer and the semiconductor substrate with the barrier layer as a mask to form a trench; forming a gate oxide layer on the inner wall of the trench; forming a polysilicon layer on the barrier layer, filling up the trench; etching back the polysilicon layer with the barrier layer mask to remove the polysilicon layer on the barrier layer to form a trench gate; removing the barrier layer and the oxide layer; implanting ions into the semiconductor substrate on both sides of the trench gate to form a diffusion layer; coating a photoresist layer on the diffusion layer and defining a source/drain layout thereon; implanting ions into the diffusion layer based on the source/drain layout with the photoresist layer mask to form the source/drain; forming sidewalls on both the sides of the trench gate after removing the photoresist layer; and forming a metal silicide layer on the diffusion layer and the trench gate. Effective result of the present invention is achieved with lower cost and improved efficiency of fabrication.

    Abstract translation: 制造沟槽DMOS晶体管的方法包括：在半导体衬底上依次形成具有光刻布局的氧化物层和阻挡层; 用阻挡层蚀刻氧化物层和半导体衬底作为掩模以形成沟槽; 在沟槽的内壁上形成栅极氧化层; 在阻挡层上形成多晶硅层，填充沟槽; 用阻挡层掩模蚀刻多晶硅层以去除阻挡层上的多晶硅层以形成沟槽栅极; 去除阻挡层和氧化物层; 在沟槽栅极的两侧将离子注入到半导体衬底中以形成扩散层; 在所述扩散层上涂覆光致抗蚀剂层并在其上限定源极/漏极布局; 基于具有光致抗蚀剂层掩模的源极/漏极布局将离子注入到扩散层中以形成源极/漏极; 在去除光致抗蚀剂层之后在沟槽栅极的两侧形成侧壁; 以及在扩散层和沟槽栅上形成金属硅化物层。 本发明的有效结果是以更低的成本和更高的制造效率实现的。

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